参数资料
型号: DS2715Z+T&R
厂商: Maxim Integrated Products
文件页数: 14/17页
文件大小: 0K
描述: IC NIMH CHARGER 16-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 充电管理
电池化学: 镍金属氢化物
电源电压: 4.5 V ~ 16 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC
包装: 带卷 (TR)
DS2715: NiMH Battery Pack Charge Controller
The R T resistor (R5) is set to 47k ? for a timeout of 70 minutes. This would be appropriate for cells with a capacity
of about 1Ah when charged with the 1.07A charge current. The resistor divider with R12 and R13 is configured to
present the voltage equivalent to a single cell on the Vbatt pin.
The value of L1 in the example represents a moderate switching speed of 100-150khz for fast-charge mode. L1
may be adjusted to fit specific application goals as long as the associated change in switching speed does not
exceed the circuit’s ability to maintain proper regulation of the sense resistor voltage. Since TOPOFF and
PRECHARGE modes have a faster switching frequency than FAST-CHARGE, the regulation in these modes must
be considered.
All capacitors should be ceramic surface mount types of good quality where possible. The 47uF capacitor may be
any type that meets the application requirements. A different network for C1 and C2 may be necessary depending
on the types of capacitors used, the layout, and the transient requirements of the application load. All resistors not
previously mentioned are standard surface mount types.
Linear
Figure 6 shows a typical application circuit for charging a 3-cell stack in linear mode. The Mode pin is tied to V SS for
linear operation. A 250m ? sense resistor (R7) sets the charge current to .484A, which the DS2715 regulates by
controlling the V GS of Q1 through the bias resistor R3. The bias resistor should be chosen so that the current that
V CH is required to sink does not exceed 20mA when V CH is fully turned on. The preferred design target for FAST-
CHARGE conditions is 10mA. The RC network of R3 and C5 set a pole in the control loop to ensure stability.
Figure 6. TYPICAL Linear APPLICATION CIRCUIT FOR A 3-CELL STACK
D1
LOAD
D2 R2 220
+6VDC
B340A-13
Vbatt
C1 C2
47 uF 1 uF
R1
150
C3
.1 uF
C5 4.7 uF
LED1 R3 470
R4 470
LED1
Vdd
Rt
R5 86K
Q1
IRF9Z24
U1
DS2715
Vch
Div
R10
R12
200K
R13
100K
THM
Q2
2N7002
R8
10k
C4
0.1 uF
SNS+
Cbias
Mode
VSS CTG SNS-
10K
THM1
10K
R7 0.25
A lower charge current is used for linear mode, in addition to a lower supply voltage. This reduces the power
dissipation of Q1 to a manageable level. This dissipation must be closely considered in the application and proper
heatsinking precautions must be taken. Different transistors may be selected for Q1 based on package size and
thermal requirements. An 86k ? resistor on R T (R5) sets the FAST-CHARGE timeout to about 129 minutes, which
for the given charge rate is appropriate for cells of about .9Ah capacity. The other aspects of the circuit are
equivalent to those of the switchmode circuit.
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