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参数资料
| 型号： | DS2726G+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC PROT LI+ 5-10CELL 32-TQFP |
| 标准包装： | 2,500 |
| 功能： | 过压/欠压保护 |
| 电池化学： | 锂离子（Li-Ion） |
| 电源电压： | 5 V ~ 50 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（7x7） |
| 包装： | 带卷 (TR) |
5-Cell to 10-Cell Li+ Protector with
Cell Balancing
Configuration of Overvoltage
Threshold
The DS2726 allows the OV threshold to be set using the
overvoltage select pins. The OV threshold is configured
using the OVS0 and OVS1 pins according to Table 3.
Enabling Cell Balancing
For cell balancing to begin the DS2726 must detect a
charger. The charge-balancing configuration pin
(CBCFG) controls how the IC detects a charger. If
CBCFG is pulled to GND, balancing is enabled when
the charge-current comparator detects a charger. This
detection occurs when V PKP > V VIN + V CDET . If CBCFG
is pulled to V CC , cell balancing is enabled when the
SLEEP pin is driven to a logic-high state. Note that cell
balancing must be enabled and a valid cell-balancing
voltage must exist for cell balancing to occur.
Configuration of Cell-Balancing
Voltage Threshold
The DS2726 allows the cell-balancing threshold to be set
using the cell-balance select pins. The threshold is config-
ured using the CBS0 and CBS1 pins according to Table 4.
Setting the cell-balancing voltage threshold to zero dis-
ables the cell-balancing circuitry. The nominal cell-bal-
Table 3. OV Threshold Configuration
ancing voltage is never allowed a value below 3.75V.
Setting the OVS0 and OVS1 pins low while the CBS0
and CBS1 pins are high results in a cell-balancing volt-
age (V BAL ) of 3.75V.
Nominal Cell-Balancing Voltage:
V BAL = V OV – Cell-Balancing Voltage Threshold
Balancing begins when any cell’s voltage is greater
than V BAL . When the balancing condition is met and
cell balancing is enabled, the corresponding internal
FET (from V x to V x-1 ) is enabled, shunting a portion of
the charge current around the cell. The external resis-
tors on V00–V10 should be chosen to limit the balanc-
ing current to a maximum of 200mA. This prevents
damaging the internal cell-balancing FETs.
The DS2726 has three distinct states during balancing.
A voltage measurement state of 5/32 t OCD time periods
is followed by a balancing state where even numbered
cells are balanced for 123/32 t OCD time periods.
Another voltage measurement state of 5/32 t OCD time
periods then occurs. This is followed by a balancing
state where odd numbered cells are balanced for
123/32 t OCD time periods. This gives an average bal-
ancing current of approximately half the maximum bal-
ance current. Cell balancing terminates when all cell
voltages are greater than V BAL . See the Measurement
Sequence section.
PIN
4.10
4.15
4.20
NOMINAL OV THRESHOLD (V)
4.25 4.30 4.35
4.40
4.45
4.50
OVS0
OVS1
V IL
V IL
V IM
V IL
V IH
V IL
V IL
V IM
V IM
V IM
V IH
V IM
V IL
V IH
V IM
V IH
V IH
V IH
Table 4. Cell-Balancing Threshold Configuration
PIN
0.00
CELL-BALANCING VOLTAGE THRESHOLD (OFFSET FROM V OV ) (V)
0.05 0.10 0.15 0.20 0.25 0.30 0.35
0.40
CBS0
CBS1
V IL
V IL
V IM
V IL
V IH
V IL
V IL
V IM
V IM
V IM
V IH
V IM
V IL
V IH
V IM
V IH
V IH
V IH
12
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