参数资料
型号: DS2745U+T&R
厂商: Maxim Integrated Products
文件页数: 10/15页
文件大小: 0K
描述: IC BATT MONITOR I2C 8-UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 3,000
功能: 燃料,电量检测计/监控器
电池化学: 锂离子(Li-Ion);镍金属氢化物(NiMH)
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-uMAX
包装: 带卷 (TR)
DS2745 Low-Cost I 2 C Battery Monitor
CURRENT BLANKING
The Current Blanking feature modifies current measurement result prior to being accumulated in the ACR. Current
Blanking occurs conditionally when a current measurement (raw current + COBR) falls in one of two defined
ranges. The first range prevents charge currents less than 100 ? V from being accumulated. The second range
prevents discharge currents less than 25 ? V in magnitude from being accumulated. Charge current blanking is
always performed, however, discharge current blanking must be enabled by setting the NBEN bit in the
Status/Config register. See the register description for additional information.
ACCUMULATION BIAS
The Accumulation Bias register (ABR) allows a programmable offset value to be added to the current accumulation
process. The new ACR value results from the addition of the Current register value plus ABR plus the previous
ACR value. ABR can be used to intentionally skew the current accumulation to estimate system stand-by currents
that are too small to measure. ABR value is not subject to the Current Blanking thresholds.
Read and write access is allowed to the ABR. Whenever the ABR is written, the new value is applied to all
subsequent current measurements. ABR can be set to any value between +198.1 ? V and -199.7 ? V in 1.56 ? V
steps. The ABR value is stored as a two’s complement value in volatile memory, and must be initialized via the
interface on power-up. Figure 9 describes the ABR address, format, and resolution.
Figure 9. ACCUMULATION BIAS REGISTER FORMAT
Address 62
S
2 6
2 5
2 4
2 3
2 2
2 1
2 0
MSb
LSb
“S”: sign bit
Units:
1.56 ? V/Rsns
MEMORY
The DS2745 has memory space with registers for instrumentation, status, and control. When the MSB of a two-
byte register is read, both the MSB and LSB are latched and held for the duration of the read data command to
prevent updates during the read and ensure synchronization between the two register bytes. For consistent results,
always read the MSB and the LSB of a two-byte register during the same read data command sequence.
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