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参数资料
| 型号： | DS2746G+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/17页 |
| 文件大小： | 0K |
| 描述： | IC MON BATTERY 2-WIRE 10-TDFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 燃料，电量检测计/监控器 |
| 电池化学： | 锂离子（Li-Ion）；镍金属氢化物（NiMH） |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 供应商设备封装： | 10-TDFN-EP（3x3） |
| 包装： | 带卷 (TR) |
DS2746 Low-Cost 2-Wire Battery Monitor
SCL, SDA
V PIN = 0.4V
Input Capacitance:
SCL, SDA
C BUS
50
pF
Bus Low Timeout
t SLEEP
(Note 3)
1.5
2.2
S
DC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(V DD = 2.5V to 4.5V, T A = -20°C to +70°C.)
PARAMETER
SCL Clock Frequency
SYMBOL
f SCL
CONDITIONS
(Note 4)
MIN
0
TYP
MAX
400
UNITS
KHz
Bus Free Time Between a
STOP and START Condition
t BUF
1.3
μs
Hold Time (Repeated)
START Condition
Low Period of SCL Clock
High Period of SCL Clock
Setup Time for a Repeated
START Condition
t HD:STA
t LOW
t HIGH
t SU:STA
(Note 5)
0.6
1.3
0.6
0.6
μs
μs
μs
μs
Data Hold Time
Data Setup Time
Rise Time of Both SDA and
SCL Signals
Fall Time of Both SDA and
SCL Signals
Setup Time for STOP
Condition
Spike Pulse Widths
Suppressed by Input Filter
Capacitive Load for Each Bus
Line
SCL, SDA Input Capacitance
t HD:DAT
t SU:DAT
t R
t F
t SU:STO
t SP
C B
C BIN
(Note 6, 7)
(Note 6)
(Note 8)
(Note 9)
0
100
20 + 0.1C B
20 + 0.1C B
0.6
0
0.9
300
300
50
400
60
μs
ns
ns
ns
μs
ns
pF
pF
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
All voltages are referenced to V SS .
Offset specified after auto-calibration cycle and Current Offset Bias register = 0x00.
The DS2746 enters the sleep mode 1.5s to 2.2s after ( SCL < V il .) AND ( SDA < V il ).
Timing must be fast enough to prevent the DS2746 from entering sleep mode due to bus low for period > t SLEEP .
f SCL must meet the minimum clock low time plus the rise/fall times.
The maximum t HD:DAT has only to be met if the device does not stretch the LOW period (t LOW ) of the SCL signal.
This device internally provides a hold time of at least 100ns for the SDA signal (referred to the VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
C b – total capacitance of one bus line in pF.
The AIN GERR spec is only valid when this equation is satisfied: (V AINx + 2V OUT ) ? (11.6V - (T A - 25 ? C)10mV/ ? C). See Figure 1.
Accuracy specification valid for V SS - SNS ≥ ±2.5mV, below which offset error is dominant.
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相关代理商/技术参数 |
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| DS2746K | 功能描述:电源管理IC开发工具 RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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| DS2751 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Multichemistry Fuel Garge |
| DS2751+ | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Multichemistry Fuel Garge |
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