参数资料
型号: DS2762AE+
厂商: Maxim Integrated Products
文件页数: 14/25页
文件大小: 0K
描述: IC MON BATT LI-ION HP 16-TSSOP
产品培训模块: 1-Wire Communications
Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 96
功能: 电池监控器
电池化学: 锂离子(Li-Ion)
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 管件
DS2762 High-Precision Li+ Battery Monitor With Alerts
Temperature Interrupt High Threshold
Address 84
2
2
2
2
2
2
2
S
6
5
4
3
2
1
0
MSb
LSb
Units: 1.0°C
Temperature Alarm Low Threshold
Address 85
2
2
2
2
2
2
2
S
6
5
4
3
2
1
0
MSb
LSb
Units: 1.0°C
POWER SWITCH INPUT
The DS2762 provides a power control function that uses the discharge protection FET to gate battery power to the
system. The PS pin, internally pulled to V DD through a 1 m A current source, is continuously monitored for a low-
impedance connection to V SS . If the DS2762 is in sleep mode, the detection of a low on the PS pin causes the
device to transition into active mode, turning on the discharge FET. If the DS2762 is already in active mode, activity
on PS has no effect other than the latching of its logic low level in the PS bit in the special feature register. The
reading of a 0 in the PS bit should be immediately followed by writing a 1 to the PS bit to ensure that a subsequent
low forced on the PS pin is latched into the PS bit.
MEMORY
The DS2762 has a 256-byte linear address space with registers for instrumentation, status, and control in the lower
32 bytes, with lockable EEPROM and SRAM memory occupying portions of the remaining address space. All
EEPROM memory is general purpose except addresses 30h, 31h, and 33h, which should be written with the
default values for the protection register, status register, and current offset register, respectively. All SRAM memory
is general purpose. When the MSB of any two-byte register is read, both the MSB and LSB are latched and held for
the duration of the read data command to prevent updates during the read and ensure synchronization between
the two register bytes. For consistent results, always read the MSB and the LSB of a two-byte register during the
same read data command sequence.
EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow the data to
be verified by the host system before being copied to EEPROM. All reads and writes to/from EEPROM memory
actually access the shadow RAM. In unlocked EEPROM blocks, the write data command updates shadow RAM. In
locked EEPROM blocks, the write data command is ignored. The copy data command copies the contents of
shadow RAM to EEPROM in an unlocked block of EEPROM but has no effect on locked blocks. The recall-data
command copies the contents of a block of EEPROM to shadow RAM regardless of whether the block is locked or
not.
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