参数资料
型号: DS2790E+
厂商: Maxim Integrated Products
文件页数: 26/41页
文件大小: 0K
描述: IC FUEL GAUGE BATT 28TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
功能: 燃料,电量检测计/监控器
电池化学: 锂离子(Li-Ion)
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
DS2790 Programmable 1-Cell Li-Ion Fuel Gauge and Protector
Figure 9. 2-Wire Slave Configuration Register (TWSCFG)
FIELD
ADDR
reserved
BIT
15:9
8:5
FORMAT
R/W
R
ALLOWABLE VALUES
2-Wire Slave Address.
Default = 0001011b
Reserved bits read as 0000b
Lengthen Timeouts. Only valid if T TIMEOUT or T LOW:SEXT timout is
enabled.
TOUT_LONG
TLS_DIS
TTO_DIS
4
3
2
R/W
R/W
R/W
0 = T LOW:SEXT – Nominal 15ms
T TIMEOUT – Nominal 30ms
1 = T LOW:SEXT – Nominal 60ms
T TIMEOUT – Nominal 120ms
T LOW:SEXT Disable
0 = T LOW:SEXT timeout is enabled
1 = T LOW:SEXT timeout is disabled
T TIMEOUT Disable
0 = T TIMEOUT is enabled
1 = T TIMEOUT is disabled
Only valid if CMD_HS_DIS = 0.
0 = (CE) Clock Extend until command register release latch is
CMD_HM
1
R/W
cleared or clock extend timeout.
1 = (NACK) Nack the command byte if command register
release latch is clear.
Command Handshake Mode Disable.
CMD_HM_DIS
0
R/W
0 = Command Handshake Mode is enabled.
1 = Command unconditionally accepted.
Note: The peripheral handles clock extension and Ack/Nack generation without intervention from the MAXQ20 core. Bus timeout conditions
detailed in the 2-Wire Specification, T TIMEOUT and T LOW:SEXT , are also handled directly by the TWS hardware.
Command Register and Handshaking
During a write, the first byte after the slave address is the command byte. The command byte signifies how the
data following the command byte should be interpreted. It is useful for software to have access to this command
byte during the entire 2-wire transaction. Therefore, the command byte is stored in the Command Register
(TWSCMD) and handshaking between the 2-wire master and CPU is implemented to ensure that the command
byte has been processed by the CPU before a new command byte can be received. Handshaking is configured in
the 2-wire Configuration Register (TWSCFG); and the following handshaking modes can be implemented:
?
?
?
CMD_HM_DIS=1, CMD_HM=X Handshaking disabled. All new command bytes are unconditionally
written to the TWSCMD register and acknowledged (ACK) by the 2-wire hardware.
CMD_HM_DIS=0, CMD_HM=0 Upon receipt of a new command byte, the TWSCMD register becomes
“busy”. The TWSCMD register will remain busy and can not accept a new command byte until the CPU
executes a “dummy” write to the TWSCMD register. The dummy write clears the busy state of the
TWSCMD register so that it can accept a new command byte. If the master attempts to send additional
command bytes while the TWSCMD register is busy, the 2-wire hardware will begin clock extending;
which will continue until the CPU executes a dummy write to the TWSCMD register or the SMBus
timeout limits are reached (if enabled).
CMD_HM_DIS=0, CMD_HM=1 In this mode, If the master attempts to send additional command bytes
while the TWSCMD register is busy, the 2-wire hardware will not acknowledge (NACK) the command
byte. The master can re-attempt to send the command byte until it is ACK’ed.
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