参数资料
型号: DS3144DK
厂商: Maxim Integrated Products
文件页数: 3/20页
文件大小: 0K
描述: KIT DEMO FOR DS3144
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 电信,调帧器
已用 IC / 零件: DS3144
已供物品: 主板和子卡组套
DS3144 DS3/E3 Framer Demo Kit Daughter Card
LINE-SIDE CONNECTIONS
The DS3144DK implements the transmit (Tx) and receive (Rx) line interface networks recommended in the
DS3154 data sheet. The BNC connectors are labeled TX1 through TX4 and RX1 through RX4. Note that the
purpose of the DS3144DK is to evaluate the DS3144 framer, not the DS3154 LIU. The DS3144DK is not an
impedance-matched board and therefore has not been designed to have transmit waveforms with optimal template
fit. To evaluate the analog performance of the DS3154, request a DS3154DK demo kit.
INTERFACE CONNECTORS
Two 50-pin connectors (J14, J15) on the bottom of the DS3144DK daughter card provide the processor interface,
DS3 clock, and power supply from the DK101 or DK2000 motherboards. These connectors also provide a
bidirectional clock/data/sync connection with the DK2000.
CONNECTION TO A COMPUTER
Refer to the DK101 data sheet or the DK2000 data sheet for information. After power is applied, if the DS3144DK
is working correctly, the FPGA status LED (green) is lit, the INT LED (red) on the DS3144DK is not lit, and the
RLOS and ROOF LEDs (red) may or may not be lit.
QUICK SETUP (REGISTER VIEW)
1)
2)
3)
4)
5)
Connect the DS3144DK daughter card to the DK101 motherboard or the DK2000 motherboard.
Connect the motherboard to a PC and a power supply as described in the motherboard data sheet.
Install and run the ChipView software, as described in the motherboard data sheet.
ChipView offers a choice between Register View, Demo, and Terminal Mode. Select Register View.
In the Definition File Assignment window, select the file DS3144DC_FPGA.def. This definition file will, in turn,
transmitting a 2 - 1 PRBS pattern. Toggle BCR1:RESYNC high then low to resynchronize the BERT receiver.
load DS3154DC.def, DS3144_1_DC.def, DS3144_2_DC.def, DS3144_3_DC.def, and DS3144_4_DC.def.
6) Next the Register View Screen appears, showing the register names, acronyms, and values for the DS3144,
DS3154, and the FPGA. Select among the register views using the pulldown menu box on the right.
Several register initialization (.INI) files are available for the DS3144DK. Initialization files are loaded by selecting
the menu option File ? Register .INI File ? Load .INI File.
7) Load the .INI file DS3144_1_txPRBS215-1_Cbit.ini.
8) Switch to the DS3154 register view (DS3154DC.def) and set TCR1 = 0 and RCR1 = 0 on the DS3154 (this
clears the transmit tri-state and receive tri-state bits that are set on power-up in the DS3154).
9) Loopback port 1 by either (a) connecting a length of coax cable between the TX1 BNC and the RX1 BNC, or
(b) setting the GCR1:LLB (local loopback) bit in the DS3154.
10) Switch to the DS3144 port 1 register view (DS3144_1_DC.def). Toggle BCR1:TC high then low to begin
15
11) At this point the following may be observed:
The port 1 BSR:SYNC bit is set, indicating the BERT receiver is receiving the 2
- 1 PRBS pattern.
·
·
Port 1 RLOS and ROOF LEDs are not lit, meaning the port 1 framer has acquired frame sync. This can
also be observed in the port 1 T3E3SR status register.
15
This is a very basic setup designed to build familiarity with the DS3144DK. Many other configurations are possible.
Consult the DS3144 data sheet and the remainder of this data sheet for further information.
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