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Figure 8-12. Interrupt Signal Flow
GLOBAL LATCHED
STATUS REGISTER
AND INTERRUPT
ENABLE REGISTER
INT*
GLOBAL.SRL bit
GLOBAL.SRIE bit
GLOBAL INTERRUPT
STATUS REGISTER
AND INTERRUPT
ENABLE REGISTER
GLOBAL.ISR bit
GLOBAL.ISRIE bit
BLOCK LATCHED
STATUS REGISTER
AND INTERRUPT
ENABLE REGISTER
block SRL bit
block SRIE bit
PORT INTERRUPT
STATUS REGISTER
AND INTERRUPT
ENABLE REGISTER
PORT.ISRIE bit
PORT.ISR bit
PORT.ISRIE bit
PORT.SRL bit
PORT LATCHED
STATUS REGISTER
AND INTERRUPT
ENABLE REGISTER
PORT.SRIE bit
PORT.SRL bit
PORT.SRIE bit
block SRL bit
block SRIE bit
GLOBAL.SRL bit
GLOBAL.SRIE bit
GLOBAL.ISRIE bit
GLOBAL.ISR bit
8.11 Reset and Power-Down
When only the hardware interface is enabled (
IFSEL = 000 and
HW = 1), the device is can be reset via the
RSTpin. The transmitters of all ports can be powered down using the
TPD pin, while the receivers of all ports can be
powered down using the
RPD pin.
When a microprocessor interface is enabled (
IFSEL≠ 000), the device presents a number of reset and power down
options. The device can be reset at a global level via the
GLOBAL.CR1:RST bit or the
RST pin, and at the port
level via the
PORT.CR1:RST bit. Each port can be powered down via the
PORT.CR1:TPD and RPD bits. The
JTAG logic is reset by the
The external
RST pin and the global reset bit
(GLOBAL.CR1:RST) are combined to create an internal global reset
signal. The global reset signal resets all the status and control registers on the chip (except the
GLOBAL.CR1:RST
bit), to their default values. It also resets all flip-flops in the global logic (including the CLAD block) and port logic to
their reset values. The
GLOBAL.CR1:RST bit stays set after a one is written to it. It is reset to zero when a zero is
written to it or when the external
RST pin is active.
At the port level, the global reset signal combines with the port reset bit
(PORT.CR1:RST) to create a port reset
signal. The port reset signal resets all the status and control registers in the port (except
PORT.CR1:RST bit) to
their default values. It also resets all flip-flops in the port logic to their reset values. The port reset bit
(
PORT.CR1:RST) stays set after a one is written to it. It is reset to zero when a zero is written to it or when the
global reset signal is active.
The data path reset (RSTDP) resets all of the same registers and flip-flops as the “general” reset (RST), except for
the control registers. This allows the device to be programmed while the data path logic is in reset. It is
recommended that a port be placed in data path reset during configuration changes.
The global data path reset bit (
GLOBAL.CR1:RSTDP) is set to one when the global reset signal is active. This bit is
cleared when a zero is written to it while the global reset signal is inactive. The global data path reset resets all of
the data path registers and flip-flops on the chip.
The port data path reset bit (
PORT.CR1:RSTDP) is set to one when the port reset signal is active. It is cleared
when a zero is written to it while the port reset signal is inactive. The port data path reset resets all of the port logic
data path registers and flip-flops.