
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Rev: 063008
22 of 375
PACKAGE PINS
NAME
256
144
TYPE
FUNCTION
D5/
SPI_SWAP
L8
J5
IOz
Data Bit 5. Bi-directional data bit 5 of the microprocessor interface. Not
driven when
CS=1 or RST=0.
SPI_SWAP (SPI_SEL=1). Controls the address and data bit order of the
SPI interface. The R/W and B bit positions do not change.
0 = LSB is transmitted and received first. The resulting bit order is:
R/W, A7, A8, A9, A10, A11, A12, A13,
A0, A1, A2, A3, A4, A5, A6, Burst,
D0, D1, D2, D3, D4, D5, D6, D7...
1 = MSB is transmitted and received first. The resulting bit order is:
R/W, A13, A12, A11, A10, A9, A8, A7,
A6, A5, A4, A3, A2, A1, A0, Burst,
D7, D6, D5, D4, D3, D2, D1, D0…
D6/
SPI_CPHA
K9
K5
IOz
Data Bit 6. Bi-directional data bit 6 of the microprocessor interface. Not
driven when
CS=1 or RST=0.
SPI_CPHA (SPI_SEL=1). When in SPI mode, setting this bit to 1 inverts
the phase of the clock signal on SPICK. See Section
2.10 for detailed
timing and functionality information. Default setting is low.
D7/
SPI_CPOL
M9
L5
IOz
Data Bit 7. Bi-directional data bit 7 of the microprocessor interface. Not
driven when
CS=1 or RST=0.
SPI_CPOL (SPI_SEL=1). When in SPI mode, setting this bit to 1 inverts
the clock signal on SPICK. See Section
2.10 for detailed timing and
functionality information. Default setting is low.
CS
J8
J3
I
Chip Select. This pin must be taken low for read/write operations. When
CS is high, the RD/DS and WR signals are ignored.
RD/DS
J9
—
I
Read Data Strobe (Intel Mode). The device drives the data bus with the
contents of the addressed register while
RD and CS are both low.
Data Strobe (Motorola Mode). Used to latch data through the
microprocessor interface.
DS must be low during read and write
operations.
WR/RW
J10
—
I
Write (Intel Mode). The device captures the contents of the data bus on
the rising edge of
WR and writes them to the addressed register location.
CS must be held low during write operations.
Read Write (Motorola Mode). Used to indicate read or write operation.
R
W must be set high for a register read cycle and low for a register write
cycle.
ALE
J7
—
I
Address Latch Enable. This signal is used to internally latch an address,
allowing multiplexing of the parallel interface address and data lines.
When ALE is high, the values of the A[10:0] pins are used for read/write
operations. On the falling edge of ALE, the values of the A[10:0] pins are
latched internally, and the latched value is used for read/write operations
until the next rising edge of ALE. ALE should be tied high for non-
multiplexed address systems.
MODE
J12
—
I
Mode. Selects
RD/WR or DS strobe mode.
0 = Read/Write Strobe Mode
1 = Data Strobe Mode
INT
J11
G5
Oz
Interrupt Output. Outputs a logic zero when an unmasked interrupt event
is detected.
INT is de-asserted when all interrupts have been
acknowledged and serviced. Active low. Inactive state is configured with
SPI_SEL
J16
—
I
Parallel/SPI Interface Select
0 = Parallel Interface
1 = SPI Interface Selected