
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Rev: 063008
26 of 375
PACKAGE PINS
NAME
256
144
TYPE
FUNCTION
SRAS
A6
B5
O
SDRAM Row Address Strobe. Active-low output, used to latch the row
address on rising edge of SD_CLK. It is used with commands for Bank
Activate, Precharge, and Mode Register Write.
SCAS
B7
D5
O
SDRAM Column Address Strobe. Active low output, used to latch the
column address on the rising edge of SD_CLK. It is used with commands
for Bank Activate, Precharge, and Mode Register Write.
SWE
A7
C5
O
SDRAM Write Enable. This active low output enables write operation and
auto precharge.
SD_UDM
D7
E7
O
SDRAM Upper Data Mask. SD_UDM is an active high output mask
signal for write data. SD_UDM is updated on both edges of SD_UDQS.
SD_UDM corresponds to data on SDATA15-SDATA8.
SD_LDM
D13
E6
O
SDRAM Lower Data Mask. SD_LDM is an active high output mask signal
for write data. SD_LDM is updated on both edges of SD_LDQS. SD_LDM
corresponds to data on SDATA7-SDATA0.
SD_LDQS
C13
E8
IOz
Lower Data Strobe. Output with write data, input with read data.
SD_LDQS corresponds to data on SDATA7-SDATA0.
SD_UDQS
D8
D7
IOz
Upper Data Strobe. Output with write data, input with read data.
SD_UDQS corresponds to data on SDATA15-SDATA8.
SD_CLK
A8
O
SDRAM Clock. SD_CLK and
SD_CLK are differential clock outputs. All
address and control input signals are sampled on the crossing of the
positive edge of SD_CLK and negative edge of SD_CLK. Output (write)
data is referenced to the crossings of SD_CLK and
SD_CLK (both
directions of crossing).
SD_CLK
A9
A7
O
SDRAM Clock (Inverted). SD_CLK and
SD_CLK are differential clock
outputs. All address and control input signals are sampled on the crossing
of the positive edge of SD_CLK and negative edge of SD_CLK. Output
(write) data is referenced to the crossings of SD_CLK and
SD_CLK (both
directions of crossing).
SD_CLKEN
C4
E5
O
SDRAM Clock Enable. Active High. SD_CLKEN must be active
throughout DDR SDRAM READ and WRITE accesses.
SERIAL INTERFACE IO PINS
TDATA1
T6
L3
TDATA2
T7
—
TDATA3
P6
—
TDATA4
N9
—
TDATA5
M5
—
TDATA6
N6
—
TDATA7
N7
—
TDATA8
R9
—
TDATA9
N10
—
TDATA10
R11
—
TDATA11
N11
—
TDATA12
R12
—
TDATA13
P14
—
TDATA14
P12
—
TDATA15
N12
—
TDATA16
P11
—
O
Transmit Serial Data Output. Output on the rising edge of TCLK. The
maximum data rate is 52Mbps.
Not all serial port signals are available on all products in the device family.
Unused output pins should not be connected.
DS33X41/X42/W41/W11: TDATA5 – TDATA16 not used.
DS33X81/X82: TDATA9 – TDATA16 not used.
TCLK1/TMCLK1
R5
M3
TCLK2
P5
—
TCLK3
R8
—
TCLK4
P9
—
I
Serial Interface Transmit Clock Input (TCLK[1:8]).The clock reference
for TDATA, which is output on the rising edge of the clock. TCLK supports
gapped clocking, up to a maximum frequency of 52MHz.
Note that TCLK1 is also TMCLK1, TCLK5 is also TMCLK2. TMCLK3
and TMCLK4 are stand-alone pins.