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参数资料
| 型号： | DS3908N+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/11页 |
| 文件大小： | 0K |
| 描述： | IC POT DUAL DIGITAL 14-TDFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 接片： | 64 |
| 电阻（欧姆）： | 100k |
| 电路数： | 2 |
| 温度系数： | 标准值 50 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | I²C（设备位址） |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-WFDFN 裸露焊盘 |
| 供应商设备封装： | 14-TDFN-EP（3x3） |
| 包装： | 带卷 (TR) |
DS3908
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
_____________________________________________________________________
9
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers:
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, and start and stop conditions.
Slave Devices: Slave devices send and receive data at
the master’s request.
Bus Idle or not Busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
Start Condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the timing dia-
gram for applicable timing.
Stop Condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a stop condition. See the timing diagram for applicable
timing.
Repeated Start Condition: The master can use a
repeated start condition at the end of one data transfer to
indicate that it will immediately initiate a new data trans-
fer following the current one. Repeated starts are com-
monly used during read operations to identify a specific
memory address to begin a data transfer. A repeated
start condition is issued identically to a normal start
condition. See the timing diagram for applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold-time requirements (see Figure 2). Data is
shifted into the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (see Figure 2) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses including when it is reading
bits from the slave.
Acknowledgement (ACK and NACK): An Acknowledge-
ment (ACK) or Not Acknowledge (NACK) is always the
9th bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave dur-
ing a write operation) performs an ACK by transmitting a
zero during the 9th bit. A device performs a NACK by
transmitting a one during the 9th bit. Timing (Figure 2)
for the ACK and NACK is identical to all other bit writes.
An ACK is the acknowledgment that the device is prop-
erly receiving data. A NACK is used to terminate a read
sequence or as an indication that the device is not
receiving data.
Byte Write: A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
SDA
SCL
tHD:STA
tLOW
tHIGH
tR
tF
tHD:DAT
tSU:DAT
REPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOP
START
tBUF
NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN).
Figure 2. I2C Timing Diagram
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3911 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Temperature-Controlled, Nonvolatile, I2C Quad DAC |
| DS3911T+ | 功能描述:ADC / DAC多通道 Fast APD Bias RoHS:否 制造商:Texas Instruments 转换速率: 分辨率:8 bit 接口类型:SPI 电压参考: 电源电压-最大:3.6 V 电源电压-最小:2 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-40 |
| DS3911T+T | 功能描述:ADC / DAC多通道 Fast APD Bias RoHS:否 制造商:Texas Instruments 转换速率: 分辨率:8 bit 接口类型:SPI 电压参考: 电源电压-最大:3.6 V 电源电压-最小:2 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-40 |
| DS3920 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Fast Current Mirror |
| DS3920_1112 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Fast Current Mirror |
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