参数资料
型号: DS3988T+T&R
厂商: Maxim Integrated
文件页数: 11/23页
文件大小: 0K
描述: IC CCFL CNTRLR 8CH 48TQFP
标准包装: 2,000
类型: CCFL 控制器
频率: 40 ~ 80 kHz
电流 - 电源: 15mA
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 带卷 (TR)
8-Channel Cold-Cathode
Fluorescent Lamp Controller
RESISTOR-SET DIMMING CLOCK
EXTERNAL DIMMING CLOCK
ANALOG DIMMING
2.0V
ANALOG DIMMING
2.0V
CONTROL VOLTAGE
DPWM
SIGNAL
0.5V
BRIGHT
PSYNC (OUTPUT)
CONTROL VOLTAGE
DPWM
SIGNAL
0.5V
BRIGHT
PSYNC (OUTPUT)
22.5Hz TO 440Hz
22.5Hz TO 440Hz
RESISTOR TO SET THE
DIMMING FREQUENCY
POSC
EXTERNAL
DIMMING CLOCK
22.5Hz to 440Hz
POSC
Figure 3. DPWM Source Configuration Options
brightness. For voltages between 0.5V and 2V the duty
cycle will vary linearly between the minimum and 100%.
The internally generated DPWM signal is available at
BRIGHT
the PSYNC I/O pin (set RGSO = 0 in CR1) for sourcing
to other DS3988s, if any, in the circuit. This allows all
DS3988s in the system to be synchronized to the same
DPWM
SIGNAL
22.5Hz TO 440Hz
PSYNC (OUTPUT)
POSC
DPWM signal. The DS3988 that is generating the
DPWM signal for other DS3988s in the system is
referred to as the DPWM source.
When the DPWM signal is provided by an external
source, either from the PSYNC pin of another DS3988 or
from some other user-generated source, it is input into the
Figure 4. The DPWM Receiver Configuration
To generate the DPWM signal internally, the DS3988
requires a clock (referred to as the dimming clock) to
set the DPWM frequency. The user can supply the dim-
ming clock by setting POSCS = 1 in CR1 and applying
an external 22.5Hz to 440Hz signal at the POSC pin, or
DS3988’s clock can be generated by the DS3988’s
oscillator (set POSCS = 0 in CR1), in which case the
frequency is set by an external resistor at the POSC
pin. These two dimming clock options are shown in
Figure 3. Regardless of whether the dimming clock is
generated internally or sourced externally, the POSC1
and POSC2 bits in CR2 must be set to match the
desired dimming clock frequency.
When the DPWM signal is generated internally, its duty
cycle (and, thus, the lamp brightness) is controlled by a
user-applied analog voltage at the BRIGHT input. A
BRIGHT voltage less than 0.5V will cause the DS3988 to
operate with the minimum burst duty cycle, providing
the lowest brightness setting, while any voltage greater
than 2.0V will cause a 100% burst duty cycle (i.e., lamps
always being driven), which provides the maximum
PSYNC I/O pin of the DS3988. In this mode, the BRIGHT
and POSC inputs are disabled and should be grounded
(see Figure 4). When multiple DS3988s are used in a
design, DS3988s configured to use externally generated
DPWM signals are referred to as DPWM receivers.
Lamp Frequency Configuration
The DS3988 can generate its own lamp frequency clock
internally (set LFSS = 0 in CR1), which can then be
sourced to other DS3988s if required, or the lamp clock
can be supplied from an external source (set LFSS = 1 in
CR1). When the lamp clock is internally generated, the
frequency (40kHz to 80kHz) is set by an external resistor
at the LOSC. In this case, the DS3988 can act as a lamp
frequency source because the lamp clock is output at
the LSYNC I/O pin for synchronizing any other DS3988s
configured as lamp frequency receivers.
The DS3988 acts as a lamp frequency receiver when
the lamp clock is supplied externally. In this case, a
40kHz to 80kHz clock must be supplied at the LSYNC
I/O. The external clock can originate from the LSYNC
I/O of a DS3988 configured as a lamp frequency
source or from some other source.
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11
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