参数资料
型号: DS8005-KIT#
厂商: Maxim Integrated Products
文件页数: 10/20页
文件大小: 0K
描述: EVALUATION KIT FOR DS8005
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 接口,模拟前端(AFE)
已用 IC / 零件: DS8005
已供物品:
相关产品: DS8005-RRX+-ND - SMART CARD AFE DUAL 28SOIC
其它名称: 90-08005#KIT
DS8005
Smart Card Interface
18
______________________________________________________________________________________
Applications Information
Performance can be affected by the layout of the appli-
cation. For example, an additional cross-capacitance of
1pF between card reader contacts C2 (RST_) and C3
(CLK_) or C2 (RST_) and C7 (I/O_) can cause contact
C2 to be polluted with high-frequency noise from C3 (or
C7). In this case, include a 100pF capacitor between
contacts C2 and CGND.
Application recommendations include the following:
Ensure there is ample ground area around the device
and the connector; place the device very near to the
connector; decouple the VDD and VDDA lines sepa-
rately. These lines are best positioned under the con-
nector.
The device and the host microcontroller must use the
same VDD supply. Pins CLKDIV1, CLKDIV2, RSTIN,
PRES_, I/OIN, 5V/3V, 1_8V, CMDVCC, and OFF are
referenced to VDD; if pin XTAL1 is to be driven by an
external clock, also reference this pin to VDD.
Trace C3 (CLK) should be placed as far as possible
from the other traces.
The trace connecting CGND to C5 (GND) should be
straight (the two capacitors on C1 (VCC_) should be
connected to this ground trace).
Avoid ground loops between CGND and GND.
Decouple VDDA and VDD separately. If two supplies
are the same in the application, they should be con-
nected in a star on the main trace
With all these layout precautions, noise should be kept to
an acceptable level and jitter on C3 (CLK_) should be
less than 100ps. Reference layouts are available on
request.
Technical Support
For technical support, go to https://support.maxim-
ic.com/micro.
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