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参数资料
| 型号： | DS80C310-QNG+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 18/22页 |
| 文件大小： | 0K |
| 描述： | IC MCU HI SPEED 25MHZ IND 44PLCC |
| 标准包装： | 500 |
| 系列： | 80C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 25MHz |
| 连通性： | EBI/EMI，SIO，UART/USART |
| 外围设备： | 欠压检测/复位，POR |
| 输入/输出数： | 32 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 256 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-LCC（J 形引线） |
| 包装： | 带卷 (TR) |
DS80C310
5 of 22
PIN
PDIP
PLCC
TQFP
NAME
FUNCTION
29
32
26
PSEN
Active-Low Program Store Enable (Output). This signal is
commonly connected to external ROM memory as a chip enable.
PSEN is driven high when data memory (RAM) is being accessed
through the bus and during a reset condition.
30
33
27
ALE
Address Latch Enable (Output). The output functions as clock to
latch the external address LSB from the multiplexed address/data
bus on Port 0. This signal is commonly connected to the latch enable
of an external 373 family transparent latch. ALE is forced high when
the DS80C310 is in a reset condition.
31
35
29
EA
Active-Low External Access (Input). This pin must be connected to
ground for proper operation.
32
36
30
AD7(P0.7)
33
37
31
AD6(P0.6)
34
38
32
AD5(P0.5)
35
39
33
AD4(P0.4)
36
40
34
AD3(P0.3)
37
41
35
AD2(P0.2)
38
42
36
AD1(P0.1)
39
43
37
AD0(P0.0)
Address/Data Bus 0–7 (Port 0) (I/O). Port 0 is the multiplexed
address/data bus. During the time when ALE is high, the LSB of a
memory address is presented. When ALE falls to logic 0, the port
transitions to a bidirectional data bus. This bus is used to read
external ROM and read/write external RAM memory or peripherals.
Port 0 has no true port latch and cannot be written directly by
software. The reset condition of Port 0 is high.
40
44
38
VCC
+5V Power Supply
–
12, 34
6, 28
N.C.
No Connection (Reserved). These pins should not be connected.
They are reserved for use with future devices in this family.
COMPATIBILITY
The DS80C310 is a fully static, CMOS, 8051-compatible microcontroller designed for high performance.
In most cases the DS80C310 can drop into an existing socket for the 80C31 or 80C32 to significantly
improve the operation. In general, software written for existing 8051-based systems works without
modification on the DS80C310. The exception is critical timing because the high-speed microcontroller
performs its instructions much faster than the original for any given crystal selection. The DS80C310 runs
the standard 8051 family instruction set and is pin compatible with DIP, PLCC, or TQFP packages. The
DS80C310 is a streamlined version of the DS80C320. It maintains upward compatibility but has fewer
peripherals.
The DS80C310 provides three 16-bit timer/counters, a full-duplex serial port, and 256 bytes of direct
RAM. I/O ports have the same operation as a standard 8051 product. Timers default to a 12 clock-per-
cycle operation to keep their timing compatible with original 8051 family systems. However, timers are
individually programmable to run at the new 4 clocks per cycle if desired.
The DS80C310 provides several new hardware functions that are controlled by Special Function
Registers (SFRs). Table 1 summarizes the SFRs.
PERFORMANCE OVERVIEW
The DS80C310 features a high-speed 8051-compatible core. Higher speed comes not just from increasing
the clock frequency but from a newer, more efficient design.
This updated core does not have the dummy memory cycles that exist in a standard 8051. A conventional
8051 generates machine cycles using the clock frequency divided by 12. In the DS80C310, the same
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