参数资料
型号: DS80C390-QNR
厂商: DALLAS SEMICONDUCTOR
元件分类: Microcontroller
英文描述: 8-BIT, 40 MHz, MICROCONTROLLER, PQCC68
封装: PLASTIC, LCC-68
文件页数: 28/58页
文件大小: 5486K
代理商: DS80C390-QNR
DS80C390
34 of 58
110199
AC ELECTRICAL CHARACTERISTICS (Multiplexed address/data bus)
40 MHz
VARIABLE CLOCK
PARAMETER
SYMBOL MIN MAX
MIN
MAX
UNITS
Oscillator Freq.
(Ext. Osc)
1 / tCLCL
0
40
0
40
MHz
(Ext. Crystal)
1
40
1
40
ALE Pulse Width
tLHLL
0.375 tMCS - 5
ns
Port 0 Instruction Address or
4
CE0
Valid to ALE Low
tAVLL
0.125 tMCS - 5
ns
Address Hold after ALE Low
tLLAX1
0.125 tMCS - 5
ns
ALE Low to Valid Instruction In
tLLIV
0.625 tMCS - 20
ns
ALE Low to PSEN Low
tLLPL
0.125 tMCS - 5
ns
PSEN
Pulse Width
tPLPH
0.5 tMCS - 5
ns
PSEN
Low to Valid Instruction In
tPLIV
0.5 tMCS - 20
ns
Input Instruction Hold after PSEN
tPXIX
0
ns
Input Instruction Float after PSEN
tPXIZ
0.25 tMCS - 5
ns
Port 0 Address to Valid Instruction
In
tAVIV1
0.75 tMCS - 20
ns
Port 2, 4 Address to Valid
Instruction In
tAVIV2
0.875 tMCS - 25
ns
PSEN
Low to Address Float
tPLAZ
0
ns
NOTES FOR AC ELECTRICAL CHARACTERISTICS:
1. All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
2. The value tMCS is a function of the machine cycle clock in terms of the processor’s input clock
frequency. These relationships are described in the “Stretch Value Timing” table.
3. All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN , RD and WR
with 100 pF.
4. Interfacing to memory devices with float times (turn off times) over 25 ns may cause bus contention.
This will not damage the parts, but will cause an increase in operating current.
5. Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing will change in
relation to duty cycle variation.
6. Some AC timing characteristic drawings contain references to the CLK signal.
This waveform is
provided to assist in determining the relative occurrence of events, and cannot be used to determine
the timing of signals relative to the external clock.
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