参数资料
型号: DS87C520-QCL+T&R
厂商: Maxim Integrated Products
文件页数: 25/43页
文件大小: 0K
描述: IC MCU EPROM/ROM 33MHZ HS 44PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 500
系列: 87C
核心处理器: 8051
芯体尺寸: 8-位
速度: 33MHz
连通性: EBI/EMI,SIO,UART/USART
外围设备: 电源故障复位,WDT
输入/输出数: 32
程序存储器容量: 16KB(16K x 8)
程序存储器类型: OTP
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 44-LCC(J 形引线)
包装: 带卷 (TR)
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
31 of 43
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 4.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Transition Current from 1 to 0 Ports 1, 2, 3
at 2V
ITL
-800
μA
9
Input Leakage Port 0, and
EA pins, I/O
Mode
IL
-10
+10
μA
11
Input Leakage Port 0, Bus Mode
IL
-300
+300
μA
10
RST Pulldown Resistance
RRST
50
200
k
Note 1:
All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 2:
All voltages are referenced to ground.
Note 3:
Active current measured with 33MHz clock source on XTAL1, VCC = RST = 5.5V, other pins disconnected.
Note 4:
Idle mode current measured with 33MHz clock source on XTAL1, VCC = 5.5V, RST at ground, other pins
disconnected.
Note 5:
Stop mode current measured with XTAL1 and RST grounded, VCC = 5.5V, all other pins disconnected.
Note 6:
When addressing external memory. This specification only applies to the first clock cycle following the transition.
Note 7:
RST = VCC. This condition mimics operation of pins in I/O mode. Port 0 is tri-stated in reset and when at a logic high
state during I/O mode.
Note 8:
During a 0-to-1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in
transition mode.
Note 9:
Ports 1, 2, and 3 source transition current when being pulled down externally. It reaches its maximum at approximately
2V.
Note 10:
0.45 < VIN < VCC. Not a high-impedance input. This port is a weak address holding latch in Bus Mode. Peak current
occurs near the input transition point of the latch, approximately 2V.
Note 11:
0.45 < VIN < VCC. RST = VCC. This condition mimics operation of pins in I/O mode.
Note 12:
This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port
latch bit is set to 1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin will also
have to overcome the transition current.
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