参数资料
型号: DS87C520-QCL+T&R
厂商: Maxim Integrated Products
文件页数: 5/43页
文件大小: 0K
描述: IC MCU EPROM/ROM 33MHZ HS 44PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 500
系列: 87C
核心处理器: 8051
芯体尺寸: 8-位
速度: 33MHz
连通性: EBI/EMI,SIO,UART/USART
外围设备: 电源故障复位,WDT
输入/输出数: 32
程序存储器容量: 16KB(16K x 8)
程序存储器类型: OTP
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 44-LCC(J 形引线)
包装: 带卷 (TR)
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
13 of 43
setting. When desiring maximum speed, software should select a Stretch value of 0. When using very
slow RAM or peripherals, select a larger Stretch value. Note that this affects data memory only and the
only way to slow program memory (ROM) access is to use a slower crystal.
Using a Stretch value between 1 and 7 causes the microcontroller to stretch the read/write strobe and all
related timing. Also, setup and hold times are increased by 1 clock when using any Stretch greater than 0.
This results in a wider read/write strobe and relaxed interface timing, allowing more time for
memory/peripherals to respond. The timing of the variable speed MOVX is in the Electrical
Specifications section. Table 3 shows the resulting strobe widths for each Stretch value. The memory
Stretch uses the Clock Control Special Function Register at SFR location 8Eh. The Stretch value is
selected using bits CKCON.2–0. In the table, these bits are referred to as M2 through M0. The first
Stretch (default) allows the use of common 120ns RAMs without dramatically lengthening the memory
access.
Table 3. Data Memory Cycle Stretch Values
CKCON.2-0
M2
M1
M0
MEMORY CYCLES
RD OR WR STROBE
WIDTH IN CLOCKS
STROBE WIDTH
TIME at 33MHz (ns)
0
2 (forced internal)
2
60
0
1
3 (default external)
4
121
0
1
0
4
8
242
0
1
5
12
364
1
0
6
16
485
1
0
1
7
20
606
1
0
8
24
727
1
9
28
848
DUAL DATA POINTER
The timing of block moves of data memory is faster using the Dual Data Pointer (DPTR). The standard
8051 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the
DS87C520/DS83C520, this data pointer is called DPTR0, located at SFR addresses 82h and 83h. These
are the original locations. Using DPTR requires no modification of standard code. The new DPTR at SFR
84h and 85h is called DPTR1. The DPTR Select bit (DPS) chooses the active pointer. Its location is the
lsb of the SFR location 86h. No other bits in register 86h have any effect and are 0. The user switches
between data pointers by toggling the lsb of register 86h. The increment (INC) instruction is the fastest
way to accomplish this. All DPTR-related instructions use the currently selected DPTR for any activity.
Therefore it takes only one instruction to switch from a source to a destination address. Using the Dual
Data Pointer saves code from needing to save source and destination addresses when doing a block move.
The software simply switches between DPTR0 and 1 once software loads them. The relevant register
locations are as follows:
DPL
82h
Low byte original DPTR
DPH 83h
High byte original DPTR
DPL1 84h
Low byte new DPTR
DPH1 85h
High byte new DPTR
DPS
86h
DPTR Select (lsb)
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