参数资料
型号: DS89C430-QNL+
厂商: Maxim Integrated Products
文件页数: 20/46页
文件大小: 0K
描述: IC MCU FLASH 16KB 33MHZ 44-PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 26
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 33MHz
连通性: EBI/EMI,SIO,UART/USART
外围设备: 电源故障复位,WDT
输入/输出数: 32
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 管件
产品目录页面: 703 (CN2011-ZH PDF)
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers
27 of 46
External Data Memory Interface in Nonpage Mode Operation
Just like the program memory cycle, the external data memory cycle is four times slower than the internal data
memory cycle in nonpage mode. A basic internal memory cycle contains one system clock and a basic external
memory cycle contains four system clocks for nonpage mode operation.
The DS89C430 allows software to adjust the speed of external data memory access by stretching the memory bus
cycle. CKCON (8Eh) provides an application-selectable stretch value for this purpose. Software can change the
stretch value dynamically by changing the setting of CKCON.2–CKCON.0. Table 5 shows the data memory cycle
stretch values and their effect on the external MOVX memory bus cycle and the control signal pulse width in terms
of the number of oscillator clocks. A stretch machine cycle always contains four system clocks.
Table 5. Data Memory Cycle Stretch Values
RD
/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
MD2:MD0
STRETCH
CYCLES
4X/2X, CD1,
CD0 = 100
4X/2X, CD1,
CD0 = 000
4X/2X, CD1,
CD0 = X10
4X/2X, CD1,
CD0 = X11
000
0
0.5
1
2
2048
001
1
2
4
4096
010
2
4
8
8192
011
3
6
12
12,288
100
7
4
8
16
16,384
101
8
5
10
20
20,480
110
9
6
12
24
24,576
111
10
7
14
28
28,672
As Table 5 shows, the stretch feature supports eight stretched external data memory access cycles, which can be
categorized into three timing groups. When the stretch value is cleared to 000b, there is no stretch on external data
memory access and a MOVX instruction is completed in two basic memory cycles. When the stretch value is set to
1, 2, or 3, the external data memory access is extended by 1, 2, or 3 stretch machine cycles, respectively. Note
that the first stretch value does not result in adding four system clocks to the RD/WR control signals. This is
because the first stretch uses one system clock to create additional setup time and one system clock to create
additional address hold time. When using very slow RAM and peripherals, a larger stretch value (4–7) can be
selected. In this stretch category, one stretch machine cycle (4 system clocks) is used to stretch the ALE pulse
width, one stretch machine cycle is used to create additional setup, one stretch machine cycle is used to create
additional hold time, and one stretch machine cycle is added to the RD or WR strobes.
The following diagrams illustrate the timing relationship for external data memory access in full speed (stretch value
= 0), in the default stretch setting (stretch value = 1), and slow data memory accessing (stretch value = 4), when
the system clock is in divide-by-1 mode (CD1:CD0 = 10b).
相关PDF资料
PDF描述
D38999/24WF32PN CONN RCPT 32POS JAM NUT W/PINS
0355240924 1.78MM MALE 9 POS VERT BLUE
D38999/26FD19PA CONN PLUG 19POS STRAIGHT W/PINS
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