参数资料
型号: DS90CF363BMT/NOPB
厂商: National Semiconductor
文件页数: 9/15页
文件大小: 0K
描述: IC FPD-LINK TX 18BIT 48-TSSOP
标准包装: 38
类型: 发射器
驱动器/接收器数: 21/3
规程: FPD 链路,LVDS
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
封装/外壳: 48-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 48-TSSOP
包装: 管件
产品目录页面: 1280 (CN2011-ZH PDF)
其它名称: DS90CF363BMT
SNLS180D – JULY 2004 – REVISED APRIL 2013
Electrical Characteristics
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ(2)
Max
Units
IOZ
Output TRI-STATE Current
Power Down = 0V,
±1
±10
μA
VOUT = 0V or V CC
TRANSMITTER SUPPLY CURRENT
ICCTW
Transmitter Supply Current
RL = 100,
f = 25 MHz
29
40
mA
Worst Case
CL = 5 pF,
f = 40 MHz
34
45
mA
Worst Case Pattern
f = 65 MHz
42
55
mA
Typ " values are given for
V CC = 3.6V and T A =
+25°C, " Max " values are
given for V CC = 3.6V and T
A = 10°C
ICCTG
Transmitter Supply Current
RL = 100,
f = 25 MHz
28
40
mA
16 Grayscale
CL = 5 pF,
f = 40 MHz
32
45
mA
16 Grayscale Pattern
f = 65 MHz
39
50
mA
Typ " values are given for
V CC = 3.6V and T A =
+25°C, " Max " values are
given for V CC = 3.6V and T
A = 10°C
ICCTZ
Transmitter Supply Current
Power Down = Low
11
150
μA
Power Down
Driver Outputs in TRI-STATE under
Power Down Mode
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
TCIT
TxCLK IN Transition Time (Figure 6 )
5
ns
TCIP
TxCLK IN Period (Figure 7 )
14.7
T
50.0
ns
TCIH
TxCLK IN High Time (Figure 7 )
0.35T
0.5T
0.65T
ns
TCIL
TxCLK IN Low Time (Figure 7 )
0.35T
0.5T
0.65T
ns
TXIT
TxIN, and Power Down pin transition Time
1.5
6.0
ns
TXPD
Minimum pulse width for Power Down pin signal
1
us
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
LLHT
LVDS Low-to-High Transition Time (Figure 5 )
0.75
1.4
ns
LHLT
LVDS High-to-Low Transition Time (Figure 5 )
0.75
1.4
ns
TPPos0
Transmitter Output Pulse Position for Bit 0 (Figure 12 )(1)
f = 65
0.20
0
+0.20
ns
MHz
TPPos1
Transmitter Output Pulse Position for Bit 1
2.00
2.20
2.40
ns
TPPos2
Transmitter Output Pulse Position for Bit 2
4.20
4.40
4.60
ns
TPPos3
Transmitter Output Pulse Position for Bit 3
6.39
6.59
6.79
ns
TPPos4
Transmitter Output Pulse Position for Bit 4
8.59
8.79
8.99
ns
TPPos5
Transmitter Output Pulse Position for Bit 5
10.70
10.99
11.19
ns
TPPos6
Transmitter Output Pulse Position for Bit 6
12.99
13.19
13.39
ns
(1)
The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature
ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE).
Copyright 2004–2013, Texas Instruments Incorporated
3
Product Folder Links: DS90CF363B
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