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| 型号： | DSP56311VL150B1 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 72/96页 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 150MHZ 196-MAPBGA |
| 标准包装： | 630 |
| 系列： | DSP56K/Symphony |
| 类型： | 定点 |
| 接口： | 主机接口，SSI，SCI |
| 时钟速率： | 150MHz |
| 非易失内存： | ROM（576 B） |
| 芯片上RAM： | 384kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.80V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LBGA |
| 供应商设备封装： | 196-MAPBGA（15x15） |
| 包装： | 托盘 |
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DSP56311 Technical Data, Rev. 8
4-4
Freescale Semiconductor
Design Considerations
Equation 4:
The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-
case operation conditions—not necessarily a real application case. The typical internal current (ICCItyp) value
reflects the average switching of the internal buses on typical operating conditions. Perform the following steps for
applications that require very low current consumption:
1.
Set the EBD bit when you are not accessing external memory.
2.
Minimize external memory accesses, and use internal memory accesses.
3.
Minimize the number of pins that are switching.
4.
Minimize the capacitive load on the pins.
5.
Connect the unused inputs to pull-up or pull-down resistors.
6.
Disable unused peripherals.
7.
Disable unused pin activity (for example, CLKOUT, XTAL).
One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to minimize
specific board effects (that is, to compensate for measured board current not caused by the DSP). A benchmark
power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current
measurements, and the following equation to derive the current-per-MIPS value.
Equation 5:
Where:
ItypF2
=
current at F2
ItypF1
=
current at F1
F2
=
high frequency (any specified operating frequency)
F1
=
low frequency (any specified operating frequency lower than F2)
Note:
F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The
degree of difference between F1 and F2 determines the amount of precision with which the current rating
can be determined for an application.
4.4 PLL Performance Issues
The following explanations should be considered as general observations on expected PLL behavior. There is no
test that replicates these exact numbers. These observations were measured on a limited number of parts and were
not verified over the entire temperature and voltage ranges.
4.4.1
Phase Skew Performance
The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT for a
given capacitive load on CLKOUT, over the entire process, temperature and voltage ranges. As defined in Figure 2-
2, External Clock Timing, on page 2-5 for input frequencies greater than 15 MHz and the MF
≤4, this skew is
greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10
and input frequencies greater than 10 MHz, this skew is between
1.4 ns and +3.2 ns.
I
50
10
12
–
×
3.3
×
33
×
10
6
×
5.48 mA
==
MIPS
I
MHz
I
typF2
I
typF1
–
()
F2
F1
–
(
==
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| DSP56311VL160 | 功能描述:数字信号处理器和控制器 - DSP, DSC 24 BIT DSP PBFREE RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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| DSP56321EVM | 功能描述:开发板和工具包 - 其他处理器 DSP56321EVM RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
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