参数资料
型号: DSP56854FGE
厂商: Freescale Semiconductor
文件页数: 21/60页
文件大小: 0K
描述: IC DSP 16BIT 120MHZ 128-LQFP
标准包装: 72
系列: 568xx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 120MHz
连通性: EBI/EMI,SCI,SPI,SSI
外围设备: DMA,POR,WDT
输入/输出数: 41
程序存储器容量: 32KB(16K x 16)
程序存储器类型: SRAM
RAM 容量: 16K x 16
电压 - 电源 (Vcc/Vdd): 1.62 V ~ 1.98 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 128-LQFP
包装: 托盘
56854 Technical Data, Rev. 6
28
Freescale Semiconductor
4.3 Supply Voltage Sequencing and Separation Cautions
Figure 4-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies.
Notes: 1. VDD rising before VDDIO, VDDA
2. VDDIO, VDDA rising much faster than VDD
Figure 4-2 Supply Voltage Sequencing and Separation Cautions
VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD
supply (1.8V) from the voltage generated by the 3.3V VDDIO supply, see Figure 4-3. This keeps VDD from
rising faster than VDDIO.
VDD should not rise so late that a large voltage difference is allowed between the two supplies (2).
Typically this situation is avoided by using external discrete diodes in series between supplies, as shown
in Figure 4-3. The series diodes forward bias when the difference between VDDIO and VDD reaches
approximately 2.1, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper
operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
VDDIO > VDD > (VDDIO - 2.1V)
In practice, VDDA is typically connected directly to VDDIO with some filtering.
3.3V
1.8V
Time
0
2
1
Supplies Stable
VDD
VDDIO, VDDA
DC
Power
Supp
ly
V
olt
age
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