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| 型号： | DSP56F801FA60E |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 10/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP 60MHZ 16KB FLASH 48-LQFP |
| 标准包装： | 250 |
| 系列： | 56F8xx |
| 核心处理器： | 56800 |
| 芯体尺寸： | 16-位 |
| 速度： | 60MHz |
| 连通性： | SCI，SPI |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 11 |
| 程序存储器容量： | 20KB（10K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2K x 16 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 8x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-LQFP |
| 包装： | 托盘 |
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56F801 Technical Data, Rev. 17
18
Freescale Semiconductor
VDD supply current
IDDT
6
Run7 (80MHz operation)
—120
130
mA
Run7 (60MHz operation)
—102
111
mA
Wait8
—96
102
mA
Stop
—62
70
mA
Low Voltage Interrupt, external power supply9
VEIO
2.4
2.7
3.0
V
Low Voltage Interrupt, internal power supply10
VEIC
2.0
2.2
2.4
V
Power on Reset11
VPOR
—1.7
2.0
V
1.
Since the GPIOB[2:3] signals are shared with the XTAL/EXTAL function, these inputs are not 5.5 volt tolerant.
2.
Schmitt Trigger inputs are: FAULTA0, IRQA, RESET, TCS, TCK, TMS, TDI, and TRST.
3.
Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
4.
PWM pin output source current measured with 50% duty cycle.
5.
PWM pin output sink current measured with 50% duty cycle.
6.
IDDT = IDD + IDDA (Total supply current for VDD + VDDA)
7.
Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as
inputs; measured with all modules enabled.
8.
Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads;
less than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD;
measured with PLL enabled.
9.
This low voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential as VDD
via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed under transient
conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is generated).
10. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator
drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated
unless the external power supply drops below the minimum specified value (3.0V).
11. Power
–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping
up, this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up rate is. The
internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self regulates.
Table 3-4 DC Electrical Characteristics (Continued)
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Typ
Max
Unit
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DSP56F801FA60E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Pro |
| DSP56F801FA60E | 制造商:Freescale Semiconductor 功能描述:DIGITAL SIGNAL PROCESSORLQFP3.6V |
| DSP56F801FA80 | 功能描述:数字信号处理器和控制器 - DSP, DSC 80Mhz/ 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSP56F801FA80E | 功能描述:数字信号处理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSP56F801FA80E | 制造商:Freescale Semiconductor 功能描述:IC |
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