参数资料
型号: DSPB56374AEC
厂商: Freescale Semiconductor
文件页数: 56/64页
文件大小: 0K
描述: IC DSP 24BIT 150MHZ 52-LQFP
产品变化通告: Product Discontinuation 24/Feb/2012
标准包装: 160
系列: DSP56K/Symphony
类型: 音频处理器
接口: 主机接口,I²C,SAI,SPI
时钟速率: 150MHz
非易失内存: ROM(84 kB)
芯片上RAM: 54kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.25V
工作温度: -40°C ~ 110°C
安装类型: 表面贴装
封装/外壳: 52-LQFP
供应商设备封装: 52-LQFP(10x10)
包装: 托盘
DSP56374 Data Sheet, Rev. 4.2
Signal Groupings
Freescale Semiconductor
6
4.1
Power
4.2
Ground
Dedicated GPIO
Port G3
15
Timer
3
JTAG/OnCE Port
4
Note:
1 Pins are not 5 V. tolerant unless noted.
2 Port H signals are the GPIO port signals which are multiplexed with the MOD and HREQ signals.
3 Port G signals are the dedicated GPIO port signals.
4 Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.
5 Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.
Table 4. Power Inputs
Power Name
Description
PLLA_VDD (1)
PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate
external decoupling capacitors between PLLA_VDD and PLLA_GND. PLLA_VDD requires a filter
as shown in Figure 1 and Figure 2 below. See the DSP56374 technical data sheet for additional
details.
PLLP_VDD(1)
PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate
external decoupling capacitors between PLLP_VDD and PLLP_GND.
PLLD_VDD (1)
PLL Power— The voltage (1.25 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate
external decoupling capacitors between PLLD_VDD and PLLD_GND.
CORE_VDD (4)
Core Power—The voltage (1.25 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate
external decoupling capacitors.
IO_VDD
(80-pin 4)
(52-pin 3)
SHI, ESAI, ESAI_1, WDT and Timer I/O Power —The voltage (3.3 V) should be well-regulated,
and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail.
This is an isolated power for the SHI, ESAI, ESAI_1, WDT and Timer I/O. The user must provide
adequate external decoupling capacitors.
Table 5. Grounds
Ground Name
Description
PLLA_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND.
Table 3. DSP56374 Functional Signal Groupings (continued)
Functional Group
Number of
Signals1
Detailed
Description
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