参数资料
型号: DSPB56374AEC
厂商: Freescale Semiconductor
文件页数: 62/64页
文件大小: 0K
描述: IC DSP 24BIT 150MHZ 52-LQFP
产品变化通告: Product Discontinuation 24/Feb/2012
标准包装: 160
系列: DSP56K/Symphony
类型: 音频处理器
接口: 主机接口,I²C,SAI,SPI
时钟速率: 150MHz
非易失内存: ROM(84 kB)
芯片上RAM: 54kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.25V
工作温度: -40°C ~ 110°C
安装类型: 表面贴装
封装/外壳: 52-LQFP
供应商设备封装: 52-LQFP(10x10)
包装: 托盘
Signal Groupings
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
7
4.3
SCAN
4.4
Clock and PLL
PLLP_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND.
PLLD_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND.
CORE_GND(4)
Core Ground—The Core ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
IO_GND(2)
SHI, ESAI, ESAI_1, WDT and Timer I/O Ground—IO_GND is the ground for the SHI, ESAI,
ESAI_1, WDT and Timer I/O. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Table 6. SCAN Signals
Signal
Name
Type
State
During
Reset
Signal Description
SCAN
Input
SCAN—Manufacturing test pin. This pin must be connected to ground.
Table 7. Clock and PLL Signals
Signal
Name
Type
State
during
Reset
Signal Description
EXTAL
Input
External Clock / Crystal Input—An external clock source must be connected
to EXTAL in order to supply the clock to the internal clock generator and PLL.
XTAL
Output
Chip Driven Crystal Output—Connects the internal Crystal Oscillator output to an external
crystal. If an external clock is used, leave XTAL unconnected.
PINIT/NMI
Input
PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET
de-assertion and during normal instruction processing, the PINIT/NMI
Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt
(NMI) request internally synchronized to the internal system clock.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
Table 5. Grounds (continued)
Ground Name
Description
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