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参数资料
| 型号： | DSPIC30F2010T-30I/MM |
| 厂商： | Microchip Technology |
| 文件页数： | 33/49页 |
| 文件大小： | 0K |
| 描述： | IC DSPIC MCU/DSP 12K 28QFN |
| 产品培训模块： | Asynchronous Stimulus |
| 标准包装： | 1,600 |
| 系列： | dsPIC™ 30F |
| 核心处理器： | dsPIC |
| 芯体尺寸： | 16-位 |
| 速度： | 30 MIP |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | 高级欠压探测/复位，电机控制 PWM，QEI，POR，PWM，WDT |
| 输入/输出数： | 20 |
| 程序存储器容量： | 12KB（4K x 24） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 1K x 8 |
| RAM 容量： | 512 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 数据转换器： | A/D 6x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-VQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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2011 Microchip Technology Inc.
DS70118J-page 39
dsPIC30F2010
5.2
Reset Sequence
A Reset is not a true exception, because the interrupt
controller is not involved in the Reset process. The pro-
cessor initializes its registers in response to a Reset,
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory loca-
tion, immediately followed by the address target for the
GOTO
instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.
5.2.1
RESET SOURCES
In addition to External Reset and Power-on Reset
(POR), there are 6 sources of error conditions which
‘trap’ to the Reset vector.
Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an Address Pointer will cause a Reset.
Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
Brown-out Reset (BOR):
A momentary dip in the power supply to the
device has been detected, which may result in
malfunction.
Trap Lockout:
Occurrence of multiple trap conditions
simultaneously will cause a Reset.
5.3
Traps
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority as shown in Figure 5-1. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
Note that many of these trap conditions can only be
detected when they occur. Consequently, the question-
able instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: Level 8
through Level 15, which means that the IPL3 is always
set during processing of a trap.
If the user is not currently executing a trap, and he sets
the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
5.3.1
TRAP SOURCES
The following traps are provided with increasing prior-
ity. However, since all traps can be nested, priority has
little effect.
Math Error Trap:
The math error trap executes under the following four
circumstances:
1.
Should an attempt be made to divide by zero,
the divide operation will be aborted on a cycle
boundary and the trap taken.
2.
If enabled, a math error trap will be taken when
an arithmetic operation on either accumulator A
or B causes an overflow from bit 31 and the
accumulator guard bits are not utilized.
3.
If enabled, a math error trap will be taken when
an arithmetic operation on either accumulator A
or B causes a catastrophic overflow from bit 39
and all saturation is disabled.
4.
If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap will occur.
Note:
If the user does not intend to take correc-
tive action in the event of a trap error con-
dition, these vectors must be loaded with
the address of a default handler that sim-
ply contains the RESET instruction. If, on
the other hand, one of the vectors contain-
ing an invalid address is called, an
address error trap is generated.
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| DSPIC30F2010T-20I/MM | IC DSPIC MCU/DSP 12K 28QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DSPIC30F2011 | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-Bit Digital Signal Controllers |
| DSPIC30F2011_06 | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-Bit Digital Signal Controllers |
| DSPIC30F2011_08 | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-bit Digital Signal Controllers |
| dsPIC30F2011-20E/ML | 功能描述:数字信号处理器和控制器 - DSP, DSC 28LD 20MIPS 12 KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| dsPIC30F2011-20E/P | 功能描述:数字信号处理器和控制器 - DSP, DSC 18LD 20MIPS 12 KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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