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| 型号： | DSPIC30F5015-30I/PT |
| 厂商： | Microchip Technology |
| 文件页数： | 68/129页 |
| 文件大小： | 0K |
| 描述： | IC DSPIC MCU/DSP 66K 64TQFP |
| 产品培训模块： | dsPIC30F Quadrature Encoder Interface Serial Communications using dsPIC30F CAN Serial Communications using dsPIC30F I2C Serial Communications using dsPIC30F SPI Serial Communications using dsPIC30F UART dsPIC30F 12 bit ADC - Part 2 dsPIC30F Addressing Modes - Part 1 dsPIC30F Architecture - Part 1 dsPIC30F DSP Engine & ALU dsPIC30F Interrupts dsPIC30F Motor Control PWM dsPIC Timers Asynchronous Stimulus dsPIC30F Addressing Modes - Part 2 dsPIC30F Architecture - Part 2 dsPIC30F 12-bit ADC Part 1 |
| 标准包装： | 160 |
| 系列： | dsPIC™ 30F |
| 核心处理器： | dsPIC |
| 芯体尺寸： | 16-位 |
| 速度： | 30 MIP |
| 连通性： | CAN，I²C，SPI，UART/USART |
| 外围设备： | 高级欠压探测/复位，电机控制 PWM，QEI，POR，PWM，WDT |
| 输入/输出数： | 52 |
| 程序存储器容量： | 66KB（22K x 24） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 1K x 8 |
| RAM 容量： | 2K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 64-TQFP |
| 包装： | 托盘 |
| 产品目录页面： | 651 (CN2011-ZH PDF) |
| 配用： | XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP AC164319-ND - MODULE SKT MPLAB PM3 64TQFP DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE |
| 其它名称： | DSPIC30F501530IPT |
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2008 Microchip Technology Inc.
DS70149D-page 43
dsPIC30F5015/5016
5.0
INTERRUPTS
The dsPIC30F5015/5016 has 36 interrupt sources and
4 processor exceptions (traps), which must be
arbitrated based on a priority scheme.
The CPU is responsible for reading the Interrupt
Vector Table (IVT) and transferring the address
contained in the interrupt vector to the program
counter. The interrupt vector is transferred from the
program data bus into the program counter, via a
24-bit wide multiplexer on the input of the program
counter.
The Interrupt Vector Table (IVT) and Alternate
Interrupt Vector Table (AIVT) are placed near the
beginning of program memory (0x000004). The IVT
and AIVT are shown in Figure 5-1.
The
interrupt
controller
is
responsible
for
pre-processing
the
interrupts
and
processor
exceptions, prior to their being presented to the
processor core. The peripheral interrupts and traps are
enabled, prioritized and controlled using centralized
Special Function Registers:
IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
All Interrupt Request Flags are maintained in
these three registers. The flags are set by their
respective peripherals or external signals, and
they are cleared via software.
IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
All Interrupt Enable Control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
IPC0<15:0>... IPC11<7:0>
The user assignable priority level associated with
each of these 44 interrupts is held centrally in
these twelve registers.
IPL<3:0>
The current CPU priority level is explicitly stored
in the IPL bits. IPL<3> is present in the CORCON
register, whereas IPL<2:0> are present in the
STATUS register (SR) in the processor core.
INTCON1<15:0>, INTCON2<15:0>
Global interrupt control functions are derived from
these two registers. INTCON1 contains the
control and status flags for the processor
exceptions. The INTCON2 register controls the
external interrupt request signal behavior and the
use of the alternate vector table.
All interrupt sources can be user assigned to one of
seven priority levels, 1 through 7, via the IPCx
registers. Each interrupt source is associated with an
interrupt vector, as shown in Table 5-1. Levels 7 and 1
represent the highest and lowest maskable priorities,
respectively.
If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is
prevented, even if the new interrupt is of higher priority
than the one currently being serviced.
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts,
interrupt-on-change, etc. Control of these features
remains within the peripheral module which generates
the interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in program
memory that corresponds to the interrupt. There are 63
different vectors within the IVT (refer to Figure 5-2).
These vectors are contained in locations 0x000004
through 0x0000FE of program memory (refer to
Figure 5-2). These locations contain 24-bit addresses,
and in order to preserve robustness, an address error
trap will take place should the PC attempt to fetch any
of these words during normal execution. This prevents
execution of random data as a result of accidentally
decrementing a PC into vector space, accidentally
mapping a data space address into vector space or the
PC rolling over to 0x000000 after reaching the end of
implemented program memory space. Execution of a
GOTO instruction to this vector space will also generate
an address error trap.
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157).
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its
corresponding
enable
bit.
User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
Note:
Assigning a priority level of 0 to an
interrupt source is equivalent to disabling
that interrupt.
Note:
The IPL bits become read-only whenever
the NSTDIS bit has been set to ‘1’.
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