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| 型号： | DSPIC30F5015-30I/PT |
| 厂商： | Microchip Technology |
| 文件页数： | 8/129页 |
| 文件大小： | 0K |
| 描述： | IC DSPIC MCU/DSP 66K 64TQFP |
| 产品培训模块： | dsPIC30F Quadrature Encoder Interface Serial Communications using dsPIC30F CAN Serial Communications using dsPIC30F I2C Serial Communications using dsPIC30F SPI Serial Communications using dsPIC30F UART dsPIC30F 12 bit ADC - Part 2 dsPIC30F Addressing Modes - Part 1 dsPIC30F Architecture - Part 1 dsPIC30F DSP Engine & ALU dsPIC30F Interrupts dsPIC30F Motor Control PWM dsPIC Timers Asynchronous Stimulus dsPIC30F Addressing Modes - Part 2 dsPIC30F Architecture - Part 2 dsPIC30F 12-bit ADC Part 1 |
| 标准包装： | 160 |
| 系列： | dsPIC™ 30F |
| 核心处理器： | dsPIC |
| 芯体尺寸： | 16-位 |
| 速度： | 30 MIP |
| 连通性： | CAN，I²C，SPI，UART/USART |
| 外围设备： | 高级欠压探测/复位，电机控制 PWM，QEI，POR，PWM，WDT |
| 输入/输出数： | 52 |
| 程序存储器容量： | 66KB（22K x 24） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 1K x 8 |
| RAM 容量： | 2K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 64-TQFP |
| 包装： | 托盘 |
| 产品目录页面： | 651 (CN2011-ZH PDF) |
| 配用： | XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP AC164319-ND - MODULE SKT MPLAB PM3 64TQFP DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE |
| 其它名称： | DSPIC30F501530IPT |
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2008 Microchip Technology Inc.
DS70149D-page 105
dsPIC30F5015/5016
16.0 SPI MODULE
The Serial Peripheral Interface (SPI) module is a
synchronous
serial
interface.
It
is
useful
for
communicating with other peripheral devices such as
EEPROMs, shift registers, display drivers and A/D
converters, or other microcontrollers. It is compatible
with Motorola’s SPI and SIOP interfaces.
16.1
Operating Function Description
Each SPI module consists of a 16-bit Shift register,
SPIxSR (where x = 1 or 2), used for shifting data in
and out, and a Buffer register, SPIxBUF. A Control
register,
SPIxCON,
configures
the
module.
Additionally, a status register, SPIxSTAT, indicates
various status conditions.
The serial interface consists of 4 pins: SDIx (serial
data input), SDOx (serial data output), SCKx (shift
clock input or output), and SSx (active-low slave
select).
In Master mode operation, SCK is a clock output, but
in Slave mode, it is a clock input.
A series of eight (8) or sixteen (16) clock pulses shifts
out bits from the SPIxSR to SDOx pin and
simultaneously shifts in data from SDIx pin. An
interrupt is generated when the transfer is complete
and the corresponding Interrupt Flag bit (SPI1IF or
SPI2IF) is set. This interrupt can be disabled through
an Interrupt Enable bit (SPI1IE or SPI2IE).
The receive operation is double-buffered. When a
complete byte is received, it is transferred from
SPIxSR to SPIxBUF.
If the receive buffer is full when new data is being
transferred from SPIxSR to SPIxBUF, the module will
set the SPIROV bit, indicating an overflow condition.
The transfer of the data from SPIxSR to SPIxBUF will
not be completed and the new data will be lost. The
module will not respond to SCL transitions while
SPIROV is ‘1’, effectively disabling the module until
SPIxBUF is read by user software.
Transmit writes are also double-buffered. The user
writes to SPIxBUF. When the master or slave transfer
is completed, the contents of the Shift register
(SPIxSR) is moved to the receive buffer. If any
transmit data has been written to the Buffer register,
the contents of the transmit buffer are moved to
SPIxSR. The received data is thus placed in SPIxBUF
and the transmit data in SPIxSR is ready for the next
transfer.
In Master mode, the clock is generated by prescaling
the system clock. Data is transmitted as soon as a
value is written to SPIxBUF. The interrupt is generated
at the middle of the transfer of the last bit.
In Slave mode, data is transmitted and received as
external clock pulses appear on SCK. Again, the
interrupt is generated when the last bit is latched. If
SSx control is enabled, then transmission and
reception are enabled only when SSx = low. The
SDOx output will be disabled in SSx mode with SSx
high.
The clock provided to the module is (FOSC/4). This
clock is then prescaled by the primary (PPRE<1:0>)
and the secondary (SPRE<2:0>) prescale factors. The
CKE bit determines whether transmit occurs on
transition from active clock state to Idle clock state, or
vice versa. The CKP bit selects the Idle state (high or
low) for the clock.
16.1.1
WORD AND BYTE
COMMUNICATION
A control bit, MODE16 (SPIxCON<10>), allows the
module to communicate in either 16-bit or 8-bit mode.
16-bit operation is identical to 8-bit operation, except
that the number of bits transmitted is 16 instead of 8.
The user software must disable the module prior to
changing the MODE16 bit. The SPI module is reset
when the MODE16 bit is changed by the user.
A basic difference between 8-bit and 16-bit operation is
that the data is transmitted out of bit 7 of the SPIxSR for
8-bit operation, and data is transmitted out of bit 15 of
the SPIxSR for 16-bit operation. In both modes, data is
shifted into bit 0 of the SPIxSR.
16.1.2
SDOx DISABLE
A control bit, DISSDO, is provided to the SPIxCON
register to allow the SDOx output to be disabled. This
will allow the SPI module to be connected in an input
only configuration. SDO can also be used for general
purpose I/O.
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157).
Note:
The user must perform reads of SPIxBUF
if the module is used in a transmit only
configuration to avoid a receive overflow
condition (SPIROV = 1).
Note:
Both the transmit buffer (SPIxTXB) and
the receive buffer (SPIxRXB) are mapped
to the same register address, SPIxBUF.
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