参数资料
型号: DSPIC33FJ32MC204-I/ML
厂商: Microchip Technology
文件页数: 24/76页
文件大小: 0K
描述: IC DSPIC MCU/DSP 32K 44QFN
产品培训模块: Asynchronous Stimulus
特色产品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
标准包装: 45
系列: dsPIC™ 33F
核心处理器: dsPIC
芯体尺寸: 16-位
速度: 40 MIP
连通性: I²C,IrDA,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,电机控制 PWM,QEI,POR,PWM,WDT
输入/输出数: 35
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 9x10b/12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-VQFN 裸露焊盘
包装: 管件
产品目录页面: 652 (CN2011-ZH PDF)
配用: DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
DS70283K-page 30
2007-2012 Microchip Technology Inc.
4.1.1
PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
4.1.2
INTERRUPT AND TRAP VECTORS
All dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
devices reserve the addresses between 0x00000 and
0x000200 for hard-coded program execution vectors.
A hardware Reset vector is provided to redirect code
execution from the default value of the PC on device
Reset to the actual start of code. A GOTO instruction is
programmed by the user application at 0x000000, with
the actual address for the start of code at 0x000002.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
devices also have two interrupt vector tables, located
from 0x000004 to 0x0000FF and 0x000100 to
0x0001FF. These vector tables allow each of the
device interrupt sources to be handled by separate
Interrupt Service Routines (ISRs). A more detailed
discussion of the interrupt vector tables is provided in
FIGURE 4-2:
PROGRAM MEMORY ORGANIZATION
0
8
16
PC Address
0x000000
0x000002
0x000004
0x000006
23
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
least significant word
most significant word
Instruction Width
0x000001
0x000003
0x000005
0x000007
msw
Address
(lsw Address)
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