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参数资料
| 型号： | DSPIC33FJ64MC710T-I/PF |
| 厂商： | Microchip Technology |
| 文件页数： | 122/199页 |
| 文件大小： | 0K |
| 描述： | IC DSPIC MCU/DSP 64K 100TQFP |
| 产品培训模块： | Asynchronous Stimulus |
| 标准包装： | 1,000 |
| 系列： | dsPIC™ 33F |
| 核心处理器： | dsPIC |
| 芯体尺寸： | 16-位 |
| 速度： | 40 MIP |
| 连通性： | CAN，I²C，IrDA，LIN，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，DMA，电机控制 PWM，QEI，POR，PWM，WDT |
| 输入/输出数： | 85 |
| 程序存储器容量： | 64KB（64K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 16K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 24x10b/12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-TQFP |
| 包装： | 带卷 (TR) |
| 配用： | MA330013-ND - MODULE PLUG-IN DSPIC33 100TQFP DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32 AC164323-ND - MODULE SKT FOR 100TQFP |
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2007 Microchip Technology Inc.
Preliminary
DS70165E-page 27
dsPIC33F
2.0
CPU
The dsPIC33F CPU module has a 16-bit (data) modified
Harvard architecture with an enhanced instruction set,
including significant support for DSP. The CPU has a
24-bit instruction word with a variable length opcode field.
The Program Counter (PC) is 23 bits wide and
addresses up to 4M x 24 bits of user program memory
space.
The
actual
amount
of
program
memory
implemented varies by device. A single-cycle instruction
prefetch mechanism is used to help maintain throughput
and provides predictable execution. All instructions
execute in a single cycle, with the exception of
instructions that change the program flow, the double
word move (MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported
using the DO and REPEAT instructions, both of which are
interruptible at any point.
The dsPIC33F devices have sixteen, 16-bit working
registers in the programmer’s model. Each of the working
registers can serve as a data, address or address offset
register. The 16th working register (W15) operates as a
software Stack Pointer (SP) for interrupts and calls.
The dsPIC33F instruction set has two classes of
instructions: MCU and DSP. These two instruction
classes are seamlessly integrated into a single CPU.
The instruction set includes many addressing modes
and is designed for optimum C compiler efficiency. For
most
instructions,
the
dsPIC33F
is
capable
of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 2-1,
and the programmer’s model for the dsPIC33F is
shown in Figure 2-2.
2.1
Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The MCU
class of instructions operates solely through the X mem-
ory AGU, which accesses the entire memory map as one
linear data space. Certain DSP instructions operate
through the X and Y AGUs to support dual operand
reads, which splits the data address space into two parts.
The X and Y data space boundary is device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software boundary
checking overhead for DSP algorithms. Furthermore,
the X AGU circular addressing can be used with any of
the MCU class of instructions. The X AGU also supports
Bit-Reversed Addressing to greatly simplify input or
output data reordering for radix-2 FFT algorithms.
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K
program word boundary defined by the 8-bit Program
Space Visibility Page (PSVPAG) register. The program
to data space mapping feature lets any instruction
access program space as if it were data space.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers, but may
be used as general purpose RAM.
2.2
DSP Engine Overview
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier,
a
40-bit
ALU,
two
40-bit
saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value,
up to 16 bits right or left, in a single cycle. The DSP
instructions
operate
seamlessly
with
all
other
instructions and have been designed for optimal
real-time performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the
result
in
the
same
cycle.
This
instruction
functionality requires that the RAM memory data space
be split for these instructions and linear for all others.
Data space partitioning is achieved in a transparent
and flexible manner through dedicating certain working
registers to each address space.
2.3
Special MCU Features
The dsPIC33F features a 17-bit by 17-bit, single-cycle
multiplier that is shared by both the MCU ALU and DSP
engine. The multiplier can perform signed, unsigned
and mixed-sign multiplication. Using a 17-bit by 17-bit
multiplier for 16-bit by 16-bit multiplication not only
allows you to perform mixed-sign multiplication, it also
achieves accurate results for special operations, such
as (-1.0) x (-1.0).
The dsPIC33F supports 16/16 and 32/16 divide
operations, both fractional and integer. All divide
instructions are iterative operations. They must be
executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit,
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
Note:
This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
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相关代理商/技术参数 |
参数描述 |
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| dsPIC33FJ64MC802-E/MM | 功能描述:数字信号处理器和控制器 - DSP, DSC 16Bit MCU/DSP 40MIPS 64KB FLASH RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| dsPIC33FJ64MC802-E/SO | 功能描述:数字信号处理器和控制器 - DSP, DSC 16B DSC 28LD64KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| dsPIC33FJ64MC802-E/SP | 功能描述:数字信号处理器和控制器 - DSP, DSC 16B DSC 28LD64KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| dsPIC33FJ64MC802-H/MM | 功能描述:数字信号处理器和控制器 - DSP, DSC 16-bit 64KB Flash Motor CAN DMA RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| dsPIC33FJ64MC802-H/SO | 功能描述:数字信号处理器和控制器 - DSP, DSC 16-bit 64KB Flash Motor CAN DMA RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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