- 您现在的位置：买卖IC网 > PDF目录16063 > EF-DSP-PC-NL (Xilinx Inc)SOFTWARE SYS GEN FOR DSP PDF资料下载
参数资料
| 型号： | EF-DSP-PC-NL |
| 厂商： | Xilinx Inc |
| 文件页数： | 19/42页 |
| 文件大小： | 0K |
| 描述： | SOFTWARE SYS GEN FOR DSP |
| 标准包装： | 1 |
| 系列： | ISE® 设计套件 |
| 类型： | 系统发生器 |
| 适用于相关产品： | Xilinx DSPs |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页
What’s New in Xilinx ISE Design Suite 13.1
What's New in CORE Generator and IP
The following describes what's new in CORE Generator? software and IP cores:
Introducing CORE Generator IP with Virtex?-7 and Kintex?-7 support
New IP Cores
?
Audio, Video and Image Processing IP
?
Object Segmentation v1.0 (AXI4-Lite)
-
Used in conjunction with the Image Characterization LogiCORE IP to convert
statistical data provided into a list of objects that meet a user-defined set of
object characteristics.
?
AXI Video Direct Memory Access v1.0 (AXI4, AXI4-Stream, AXI4-Lite)
-
Provides a flexible interface for controlling and synchronizing video frame
stores from external memory. Multiple VDMAs from different clock domains
can be linked together to control frame store reads and writes from multiple
sources.
?
Communication DSP Building Blocks
?
Linear Algebra Toolkit v1.0 (AXI4-Stream)
-
-
Implements basic Matrix operations - Matrix-Matrix Addition, Subtraction,
Matrix-Scalar Multiplication and Matrix-Matrix Multiplication.
This IP provides flexible and optimized building blocks for developing
complex composite functions for various signal and data processing
applications.
?
FPGA Features and Support
?
-
-
Configures one or more Virtex-7 and Kintex-7 FPGA GTX transceivers either
from scratch, or using industry standard templates, using a custom Verilog or
VHDL wrapper.
Also provides an example design, testbench, and scripts to allow you to
observe the transceivers operating in simulation and in hardware.
?
-
The XADC Wizard generates an HDL wrapper to configure a single 7 Series
FPGA XADC primitive for user-specified channels and alarms.
?
Standard Bus Interfaces and I/O
?
7-Series Integrated Block for PCI Express (PCIe) v1.0 (AXI4-Stream)
-
-
Implements 1-lane, 2-lane, 4-lane, or 8-lane configurations. The IP uses the 7
Series Integrated Hard IP Block for PCI Express in conjunction with flexible
architectural features to implement a PCI Express Base Specification v2.1
compliant PCI Express Endpoint or Root Port.
Unique features of the LogiCORE IP for PCI Express are the high
performance AXI Interface, optimal buffering for high bandwidth
applications, and BAR checking and filtering.
?
Wireless IP
?
Triple Rate SDI v1.0 (AXI4-Stream)
-
Provides receiver and transmitter interfaces for the SMPTE SD-SDI, HD-SDI,
and 3G-SDI standards.
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.1)
19
相关PDF资料 |
PDF描述 |
|---|---|
| 135110-07-48.00 | CBL SMA STR PLUG-JACK RG142 48" |
| RMM08DTBS | CONN EDGECARD 16POS R/A .156 SLD |
| RGM08DTBS | CONN EDGECARD 16POS R/A .156 SLD |
| 135101-07-48.00 | CBL SMA STR PLUG-PLUG RG142 48" |
| DO-CSP-PRO-USB-II-G-NL | CHIPSCOPE PRO WITH USB-II CABLE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EFDSS645B25A | 制造商:Panasonic Industrial Company 功能描述:DELAY LINE |
| EFDST645B15B | 制造商:Panasonic Industrial Company 功能描述:DELAY LINE |
| EFE01A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|BRIDGE|HALF-CNTLD|CC|200V V(RRM) |
| EFE01A-F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|BRIDGE|HALF-CNTLD|CC|200V V(RRM) |
| EFE01A-S | 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|BRIDGE|HALF-CNTLD|CC|200V V(RRM) |
发布紧急采购，3分钟左右您将得到回复。