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参数资料
| 型号： | EF-ISE-SYSTEM-NL |
| 厂商： | Xilinx Inc |
| 文件页数： | 34/50页 |
| 文件大小： | 0K |
| 描述： | SOFTWARE ISE SYS EDITION |
| 标准包装： | 1 |
| 系列： | ISE® 设计套件 |
| 类型： | 集成软件环境（ISE） |
| 适用于相关产品： | Xilinx FPGAs |
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Chapter 2: What’s New in PlanAhead Software
Message Manager
A new Messages view consolidates error, critical warning, warning, and informational
messages from PlanAhead and ISE software tools into a single view. Messages are linked to
the source code to allow for quick exploration and resolution of any errors or warnings.
Netlist View Additions and Modifications
The following subsections describe the additions and modifications to the PlanAhead
Netlist view.
Clocking Resource View
The new Clocking Resource view enables you to visualize and assign clocking-related sites
and physical resources within the FPGA.
Folders for Component Switching Limits
There are new folders in the Timing Results view imported from TRACE that better
organize the component pin switching limit violations with setup and hold violations. The
violations are sorted and the worst violation is displayed first within a constraint.
Enhanced Slack Histogram Report
PlanAhead release 13 contains an improved slack histogram feature which creates a
graphical bar chart corresponding to collections of paths within ranges from most negative
to most positive.
Device View Enhancements
PlanAhead Release 13 contains the following enhancements.
Device Resource Details
The Device view in PlanAhead has been enhanced to provide more detail for device
resources, such as pins on slices and BEL-level pins for Virtex?-6 and Virtex-7 devices, and
the Timing Path provides annotation on pins upon full placement.
Multiple Instance Drag and Drop
PlanAhead now allows moving multiple instances in the device view at the same time.
This allows users to move instances that are already placed in a group, and all location
constraints are translated together.
Schematic View Enhancements
PlanAhead supports tracing logic between two selected objects in the Schematic view. Any
two objects can be selected, and the PlanAhead software will trace and draw any
intermediate logic connections between them within a schematic.
XPA Integration
PlanAhead has added the ability to launch Xilinx Power Analyzer (XPA) to analyze power
on implemented designs. To launch XPA, open an implemented design, and click the
XPower Analyzer icon.
34
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
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