参数资料
型号: EFM32-TG108F32-SK
厂商: Energy Micro
文件页数: 77/136页
文件大小: 0K
描述: IC MICRO KIT GECKO 24QFN
标准包装: 1
系列: Tiny Gecko
套件类型: 微控制器
值: 2 件 - 闪存 - 32KB
包装: 纸板盒
安装类型: 表面贴装
包括封装: 24-QFN
工具箱内容: (2) 914-1032-2-ND - MCU 32BIT 32KB FLASH 24-QFN
其它名称: 914-1025
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
45
www.energymicro.com
Example 3.2 (p. 45) shows the use of conditional instructions to update the value of R4 if the signed
values R0 is greater than R1 and R2 is greater than R3.
Example 3.2. Compare and update value
CMP
R0, R1
; Compare R0 and R1, setting flags
ITT
GT
; IT instruction for the two GT conditions
CMPGT
R2, R3
; If 'greater than', compare R2 and R3, setting flags
MOVGT
R4, R5
; If still 'greater than', do R4 = R5
3.3.8 Instruction width selection
There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on
the operands and destination register specified. For some of these instructions, you can force a specific
instruction size by using an instruction width suffix. The .W suffix forces a 32-bit instruction encoding.
The .N suffix forces a 16-bit instruction encoding.
If you specify an instruction width suffix and the assembler cannot generate an instruction encoding of
the requested width, it generates an error.
Note
In some cases it might be necessary to specify the .W suffix, for example if the operand
is the label of an instruction or literal data, as in the case of branch instructions. This is
because the assembler might not automatically generate the right size encoding.
To use an instruction width suffix, place it immediately after the instruction mnemonic and condition
code, if any. Example 3.3 (p. 45) shows instructions with the instruction width suffix.
Example 3.3. Instruction width selection
BCS.W
label
; creates a 32-bit instruction even for a short branch
ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same
; operation can be done by a 16-bit instruction
3.4 Memory access instructions
Table 3.5 (p. 45) shows the memory access instructions:
Table 3.5. Memory access instructions
Mnemonic
Brief description
See
ADR
Load PC-relative address
CLREX
Clear Exclusive
LDM{mode}
Load Multiple registers
LDR{type}
Load Register using immediate offset
LDR{type}
Load Register using register offset
LDR{type}T
Load Register with unprivileged access
LDR
Load Register using PC-relative address
LDREX{type}
Load Register Exclusive
POP
Pop registers from stack
PUSH
Push registers onto stack
STM{mode}
Store Multiple registers
STR{type}
Store Register using immediate offset
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