参数资料
型号: EFM32TG108F32
厂商: Energy Micro
文件页数: 17/136页
文件大小: 0K
描述: MCU 32BIT 32KB FLASH 24-QFN
特色产品: EFM32 Tiny Gecko
标准包装: 1
系列: Tiny Gecko
核心处理器: ARM? Cortex?-M3
芯体尺寸: 32-位
速度: 32MHz
连通性: EBI/EMI,I²C,IrDA,智能卡,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 17
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.8 V
数据转换器: A/D 2x12b,D/A 1x12b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 24-VQFN 裸露焊盘
包装: 标准包装
其它名称: 914-1032-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
113
www.energymicro.com
4.4.4 SysTick Calibration Value Register
The CALIB register indicates the SysTick calibration properties and is a read only register. See the
register summary in Table 4.32 (p. 111) for its attributes. The bit assignments are:
31
0
TENMS
Reserved
23
24
30
SKEW
NOREF
29
Table 4.36. CALIB register bit assignments
Bits
Name
Function
[31]
NOREF
Reads as zero. Indicates that a the RTC counter bit 0 is provided as a reference clock.
[30]
SKEW
Reads as one. Calibration value for the 10ms inexact timing is not known because TENMS is not
known . This can affect the suitability of SysTick as a software real time clock.
[29:24]
-
Reserved.
[23:0]
TENMS
Read as 0x0036B0, which gives 10 ms ticks when running off a 14 MHz clock.
If calibration information is not known, calculate the calibration value required from the frequency of the
processor clock or external clock.
4.4.5 SysTick design hints and tips
The SysTick counter runs on the processor clock or bit 0 of the RTC counter value. If the clock signal in
use is stopped (e.g. in lower Energy Modes), the SysTick counter stops.
Ensure software uses aligned word accesses to access the SysTick registers.
4.5 Memory protection unit
This section describes the Memory protection unit (MPU).
The MPU divides the memory map into a number of regions, and defines the location, size, access
permissions, and memory attributes of each region. It supports:
independent attribute settings for each region
overlapping regions
export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU
defines:
eight separate memory regions, 0-7
a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
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