参数资料
| 型号： | EFM32TG108F32 |
| 厂商： | Energy Micro |
| 文件页数： | 29/136页 |
| 文件大小： | 0K |
| 描述： | MCU 32BIT 32KB FLASH 24-QFN |
| 特色产品： | EFM32 Tiny Gecko |
| 标准包装： | 1 |
| 系列： | Tiny Gecko |
| 核心处理器： | ARM? Cortex?-M3 |
| 芯体尺寸： | 32-位 |
| 速度： | 32MHz |
| 连通性： | EBI/EMI，I²C，IrDA，智能卡，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，DMA，POR，PWM，WDT |
| 输入/输出数： | 17 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 4K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.8 V ~ 3.8 V |
| 数据转换器： | A/D 2x12b，D/A 1x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-VQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 其它名称： | 914-1032-6 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
124
www.energymicro.com
Glossary
This glossary describes some of the terms used in technical documents from ARM.
Abort
A mechanism that indicates to a processor that the value associated with a
memory access is invalid. An abort can be caused by the external or internal
memory system as a result of attempting to access invalid instruction or data
memory.
Aligned
A data item stored at an address that is divisible by the number of bytes that
defines the data size is said to be aligned. Aligned words and halfwords have
addresses that are divisible by four and two respectively. The terms word-
aligned and halfword-aligned therefore stipulate addresses that are divisible
by four and two respectively.
Banked register
A register that has multiple physical copies, where the state of the processor
determines which copy is used. The Stack Pointer, SP (R13) is a banked
register.
Base register
In instruction descriptions, a register specified by a load or store instruction
that is used to hold the base value for the instruction’s address calculation.
Depending on the instruction and its addressing mode, an offset can be
added to or subtracted from the base register value to form the address that
is sent to memory.
See Also Index register.
Big-endian (BE)
Byte ordering scheme in which bytes of decreasing significance in a data
word are stored at increasing addresses in memory.
See Also Byte-invariant, Endianness, Little-endian.
Big-endian memory
Memory in which:
a byte or halfword at a word-aligned address is the most significant byte
or halfword within the word at that address
a byte at a halfword-aligned address is the most significant byte within the
halfword at that address.
See Also Little-endian memory.
Breakpoint
A breakpoint is a mechanism provided by debuggers to identify an instruction
at which program execution is to be halted. Breakpoints are inserted by the
programmer to enable inspection of register contents, memory locations,
variable values at fixed points in the program execution to test that the
program is operating correctly. Breakpoints are removed after the program
is successfully tested.
Byte-invariant
In a byte-invariant system, the address of each byte of memory remains
unchanged when switching between little-endian and big-endian operation.
When a data item larger than a byte is loaded from or stored to memory,
the bytes making up that data item are arranged into the correct order
depending on the endianness of the memory access. An ARM byte-
invariant implementation also supports unaligned halfword and word memory
accesses. It expects multi-word accesses to be word-aligned.
Cache
A block of on-chip or off-chip fast access memory locations, situated between
the processor and main memory, used for storing and retrieving copies of
often used instructions, data, or instructions and data. This is done to greatly
相关PDF资料 |
PDF描述 |
|---|---|
| P87C52X2FN,112 | IC 80C51 MCU 256 RAM 40DIP |
| LPC1224FBD64/121,1 | MCU 32BIT 48K FLASH 4K 64-LQFP |
| C8051F930-GM | IC 8051 MCU 64K FLASH 32-QFN |
| MMC2107CFCPV33 | IC MCU 33MHZ 128K FLASH 144-LQFP |
| LPC11E14FHN33/401, | IC MCU 32BIT 32K 32HVQFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EFM32TG108F32-QFN24 | 制造商:Energy Micro AS 功能描述:TINY GECKO MCU - Tape and Reel 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 24QFN |
| EFM32TG108F32-QFN24T | 制造商:Energy Micro AS 功能描述:32 BIT ARM MPU, TINY GECKO - Trays |
| EFM32TG108F32-QFN24-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 24QFN |
| EFM32-TG108F32-SK | 功能描述:IC MICRO KIT GECKO 24QFN RoHS:是 类别:套件 >> 半导体产品 - IC 元件分类 系列:Tiny Gecko 其它有关文件:NXPLOGIC2-KIT-ND Contents 标准包装:1 系列:74AUP 套件类型:逻辑 值:180 件 - 18 种值各 10 件 包装:- 安装类型:表面贴装 包括封装:6-XSON，8-XSON，8-XQFN 产品目录页面:2653 (CN2011-ZH PDF) 工具箱内容:(10) 568-4391-1-ND - IC GATE MULT-FUNC CONFIG 6-XSON(10) 568-4390-1-ND - IC CONFIG MULT-FUNC GATE 6-XSON(10) 568-4389-1-ND - IC GATE DUAL FUNCTION 8-XSON(10) 568-4388-1-ND - IC GATE DUAL FUNCTION 8-XQFN(10) 568-4387-1-ND - IC F-F D-TYPE POS EDGE 8-XSON(10) 568-4386-1-ND - IC F-F D-TYPE POS EDGE 8-XQFN(10) 568-4385-1-ND - IC CONFIG MULTI-FUNC GATE 6-XSON(10) 568-4384-1-ND - IC EX-OR GATE 3-IN 6-XSON(10) 568-4383-1-ND - IC F-F D-TYPE POS EDGE 6-XSON(10) 568-4382-1-ND - IC LATCH D-TYPE 6-XSON更多... 其它名称:NXPLOGIC2-KIT |
| EFM32TG108F32-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 24QFN |
发布紧急采购，3分钟左右您将得到回复。