
Preliminary
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2011-05-19 - d0034_Rev0.91
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The Bus Matrix accepts new transfers to be initiated by each master in each cycle without inserting any
wait-states. However, the slaves may insert wait-states depending on their internal throughput and the
clock frequency.
The Cortex-M3 and the DMA Controller, and the peripherals (not peripherals in the low frequency clock
domain) run on clocks which can be prescaled separately. When accessing a peripheral which runs on
a frequency equal to or faster than the HFCORECLK, the number of wait cycles per access, in addition
to master arbitration, is given by:
Memory Wait Cycles with Clock Equal or Faster than the HFCORECLK
Ncycles = 2 + Nslave cycles
(5.3)
where Nslave cycles is the wait cycles introduced by the slave.
When accessing a peripheral which runs on a slower clock than the HFCORECLK, wait cycles are
introduced to allow the transfer to complete on the peripheral clock. The number of wait cycles per
access, in addition to master arbitration, is given by:
Memory Wait Cycles with Clock Slower than the CPU
Ncycles = (2 + Nslave cycles) x fHFCORECLK/fHFPERCLK
(5.4)
where Nslave cycles is the wait cycles introduced by the slave.
5.3 Access to Low Energy Peripherals (Asynchronous Registers)
5.3.1 Introduction
The Low Energy Peripherals are capable of running when the high frequency oscillator and core system
is powered off, i.e. in energy modes EM2 and in some cases also EM3. This enables the peripherals to
perform tasks while the system energy consumption is minimal.
The Low Energy Peripherals are:
Liquid Crystal Display driver - LCD
Low Energy Timer - LETIMER
Low Energy UART - LEUART
Pulse Counter - PCNT
Real Time Counter - RTC
Watchdog - WDOG
Low Energy Sensor Interface - LESENSE
All Low Energy Peripherals are memory mapped, with standardized data synchronization support.
Because the Low Energy Peripherals are running on clocks asynchronous to the core clock, there are
some constraints on how register accesses are performed, as described in the following sections. The
constraints are however standardized across all Low Energy Peripherals.
5.3.1.1 Writing
Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into
the Low Energy clock domain to maintain data consistency and predictable operation. There are two
different synchronization mechanisms on the Tiny Gecko, immediate synchronization, and delayed
synchronization. Immediate synchronization is available for the RTC, LETIMER and LESENSE, and
results in an immediate update of the target registers. Delayed synchronization is used for the remaining
Low Energy Peripherals, and for these peripherals, a write operation requires 3 positive edges of the