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参数资料
| 型号： | EL4583C |
| 英文描述： | Sync Separator(同步分离器) |
| 中文描述： | 同步分离器（同步分离器） |
| 文件页数： | 12/12页 |
| 文件大小： | 203K |
| 代理商： | EL4583C |
EL4583C
Sync Separator 50% Slice S-H Filter HOUT
Description of Operation
A simplified block schematic is shown in Figure
1 The following description is intended to pro-
vide the user with sufficient information to be
able to understand the effects that the external
components and signal conditions have on the
outputs of the integrated circuit
The video signal is AC compuled to pin 4 via the
capacitor C1 nominally 01 mF The clamp circ-
cuit A1 will prevent the input signal on pin 4
going any more negative than 15V the value of
reference voltage VR1 Thus the sync tip the
most negative part of the video waveform will be
clamped at 15V The current source I1 nominal-
ly 10
mA charges the coupling capacitor during
the remaining portion of the H line approxi-
mately 58
ms for a 1575 kHz timebase From I
t
e
C
V the video time-constant can be calculat-
ed It is important to note that the charge taken
from the capacitor during video must be replaced
during the sync tip time which is much shorter
(ratio of x 125) The corresponding current to
restore the charge during sync will therefore be
an order of magnitude higher and any resistance
in series with CI will cause sync tip crushing For
this reason the internal series resistance has been
minimized and external high resistance values in
series with the input coupling capacitor should
be avoided The user can exercise some control
over the value of the input time constant by in-
troducing an external pull-up resistance from pin
2 to the 5V supply The maximum voltage across
the resistance will be VDD less 15V for black
level For a net discharge current greater than
zero the resistance should be greater than 450k
This will have the effect of increasing the time
constant and reducing the degree of picture tilt
The current source I1 directly tracks reference
current ITR and thus increases with scan rate ad-
justment as explained later
The signal is processed through an active 3 pole
filter (F1) designed for minimum ripple with con-
stant phase delay The filter attenuates the color
burst by 24 dB and eliminates fast transient
spikes without sync crushing An external filter
is not necessary The filter also amplifies the vid-
eo signal by 6 dB to improve the detection accu-
racy The filter cut-off frequency is controlled by
an external resistor from pin 1 to ground
Internal reference voltages (block VREF) with
high immunity to supply voltage variation are
derived on the chip Reference VR4 with op-amp
A2 forces pin 12 to a reference voltage of 17V
nominal Consequently it can be seen that the
external resistance RSET will determine the val-
ue of the reference current ITR The internal re-
sistance R3 is only about 6 k
X much less than
RSET All the internal timing functions on the
chip are referenced to ITR and have excellent
supply voltage rejection
To improve noise immunity the output of the 3
pole filter is brought out to pin 7 It is recom-
mended to AC couple the output to pin 8 the
video input pin In case of strong clean video sig-
nal the video input pin pin 8 can be driven by
the signal directly
Comparator C2 on the input to the sample and
hold block (SH) compares the leading and trail-
ing edges of the sync pulse with a threshold volt-
age VR2 which is referenced at a fixed level above
the clamp voltage VR1 The output of C2 initiates
the timing one-shots for gating the sample and
hold circuits The sample of the sync tip is de-
layed by 08
ms to enable the actual sample of 2
ms to be taken on the optimum section of the
sync pulse tip The acquisition time of the circuit
is about three horizontal lines The double poly
CMOS technology enables long time constants to
be achieved with small high quality on-chip ca-
pacitors The back porch voltage is similarly de-
rived from the trailing edge of sync which also
serves to cut off the tip sample if the gate time
exceeds the tip period Note that the sample and
hold gating times will track RSET through IOT
The 50% level of the sync tip is derived through
the resistor divided R1 and R2 from the sample
and held voltages VTIP and VBP and applied to
the plus input of comparator C1 This compara-
tor has built in hysteresis to avoid false trigger-
ing The output of C2 is a digital 5V signal which
feeds the CS output buffer B1 and the other in-
ternal circuit blocks the vertical back porch and
oddeven functions
9
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| EL4583CN | 功能描述:IC VIDEO SYNC SEPARATOR 16-DIP RoHS:否 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
| EL4583CS | 功能描述:IC VIDEO SYNC SEPARATOR 16-SOIC RoHS:否 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
| EL4583CS-T13 | 功能描述:IC SYNC SEPARATOR S-H 50% 16SOIC RoHS:否 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
| EL4583CS-T7 | 功能描述:IC VIDEO SYNC SEPARATOR 16-SOIC RoHS:否 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
| EL4583CSZ | 功能描述:视频 IC EL4583CSZ SYNC SEP BROADCAST QLTY RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
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