参数资料
型号: EL4583C
英文描述: Sync Separator(同步分离器)
中文描述: 同步分离器(同步分离器)
文件页数: 7/12页
文件大小: 203K
代理商: EL4583C
EL4583C
Sync Separator 50% Slice S-H Filter HOUT
Pin Description
Contd
Pin
Function
No
Name
6
Digital Ground
This is the ground return for digital buffer outputs
7
Filter Output
Output of the active 3 pole filter which has its input on pin 4 It is recommended to ac couple the
output to pin 8
8
Video Input
This input can be directly driven by the signal if it is desired to bypass the filter for example in
the case of strong clean signals This input is 6 dB less sensitive than the filter input
9
Level Output
This pin provides an analog voltage which is nominally equal to twice the sync pulse amplitude of
the video input signal applied to pin 4 It therefore provides an indication of signal strength
10
No Signal Detect
This is a digital output which goes high when either a) loss of input signal or b) the input signal
Output
level falls below a predetermined amplitude as set by RLV on pin 2 There will be several
horizontal lines delay before the output is initiated
11
BurstBack Porch
The start of back porch output is triggered on the trailing edge of normal H sync and on the rising
Output
edge of serration pulses in the vertical interval The pulse is timed out internally to produce a one-
shot output The pulse width is a function of RSET This output can be used for dc restore
functions where the back porch level is a known reference
12
RSET
The current through the resistor RSET determines the timing of the functions within the IC
These functions include the sampling of the sync pulse 50% point back porch output and the 2H
eliminator For faster scan rates the resistor needs to be reduced inversely For NTSC 157 kHz
scan rate RSET is 681k 1% RSET must be a 1% resistor
13
OddEven Output
Odd-even output is low for even field and high for odd field The operation of this circuit has been
improved for rejecting spurious noise pulses such as those present in VCR signals
14
VDD 5V
The internal circuits are designed to have a high immunity to supply variations although as with
most ICs a 01
mF decoupling capacitor is advisable
15
Horizontal Sync
This output produces only true H pulses of nominal width 5
ms The leading edge is triggered from
Output
the leading edge of the input H sync with the same prop delay as the composite sync The half
line pulses present in the input signal during vertical blanking are eliminated with an internal 2H
eliminator circuit
16
Analog Ground
This is the ground return for the signal paths in the chips RSET RF and RLV
4
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