参数资料
| 型号： | EL4584CSZ |
| 厂商： | Intersil |
| 文件页数： | 3/15页 |
| 文件大小： | 0K |
| 描述： | IC PLL VIDEO GP 36MHZ 16-SOIC |
| 标准包装： | 47 |
| 类型： | 锁相环路（PLL） |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | CMOS，TTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:1 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 36MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 5V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
| 产品目录页面： | 1247 (CN2011-ZH PDF) |
11
FN7174.3
May 9, 2008
smaller, t
θ (see “Timing Diagrams” on page 5) increases,
and if R2 increases, tθ decreases. For LDET to be low at
lock, |t
θ| < 50 ns. C
4 is used mainly to attenuate high
frequency noise from the charge pump.
Lock Time
Let = R3C3. As t increases, damping increases, but so does
lock time. Decreasing t decreases damping and speeds up
loop response, but increases overshoot and thus increases
the number of hunting oscillations before lock. Critical
damping (
ζ = 1) occurs at minimum lock time. Because
decreased damping also decreases loop stability, it is
sometimes desirable to design slightly overdamped (
ζ > 1),
trading lock time for increased stability.
PCB Layout Considerations
It is highly recommended that power and ground planes be
used in layout. The oscillator and filter sections constitute a
feedback loop and thus care must be taken to avoid any
feedback signal influencing the oscillator except at the
control input. The entire oscillator/filter section should be
surrounded by copper ground to prevent unwanted
influences from nearby signals. Use separate paths for
analog and digital supplies, keeping the analog (oscillator
section) as short and free from spurious signals as possible.
Careful attention must be paid to correct bypassing. Keep
lead lengths short and place bypass capacitors as close to
the supply pins as possible. If laying out a PCB to use
discrete components for the VCO section, care must be
taken to avoid parasitic capacitance at the OSC pins 3 and
5, and FILTER out (pin 7). Remove ground and power plane
copper above and below these traces to avoid making a
capacitive connection to them. It is also recommended to
enclose the oscillator section within a shielded cage to
reduce external influences on the VCO, as they tend to be
very sensitive to “handwaving” influences, the LC variety
being more sensitive than crystal controlled oscillators. In
general, the higher the operating frequency, the more
important these considerations are. Self contained VCXO or
VCO modules are already mounted in a shielding cage and
therefore do not require as much consideration in layout.
Many crystal manufacturers publish informative literature
regarding use and layout of oscillators which should be
helpful.
The VCO and loop filter section of the EL4583, EL4584,
EL4585 demo board can be implemented in Figures 18, 19
and 20.
TABLE 5. LC LOOP FILTER COMPONENTS (APPROXIMATE)
FREQUENCY
(MHz)
R2
(k
Ω)
R3
(k
Ω)
C3
(F)
C4
(F)
13.301
100
30
0.01
0.001
13.5
100
30
0.01
0.001
14.75
100
33
0.01
0.001
17.734
100
39
0.01
0.001
10.738
100
22
0.01
0.001
12.273
100
27
0.01
0.001
14.318
100
30
0.01
0.001
C
3
K
dKVCO
N
ω
2
n
------------------------
4.77e
5
–
() 6.05e6
()
910
() 5000
()
2
------------------------------------------------------
0.01F
==
=
(EQ. 9)
C
4
C
3
10
-------
0.0001F
==
(EQ. 10)
R
3
2N
ζω
n
K
dKVCO
------------------------
2
() 910
() 1
() 5000
()
4.77e
5
–
() 6.05e6
()
------------------------------------------------------
31.5k
Ω
==
=
(EQ. 11)
FIGURE 17. TYPICAL LOOP FILTER
TABLE 6. XTAL LOOP FILTER COMPONENTS
(APPROXIMATE)
FREQUENCY
(MHz)
R2
(k
Ω)
R3
(M
Ω)
C3
(pF)
C4
(pF)
13.301
100
4.3
68
6.8
13.5
100
4.3
68
6.8
14.75
100
4.3
68
6.8
17.734
100
4.3
68
6.8
10.738
100
4.3
68
6.8
12.273
100
4.3
68
6.8
14.318
100
4.3
68
6.8
EL4584
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EL4584CSZ-EVAL | 功能描述:时钟和定时器开发工具 EL4584CSZ-EVAL EVALUATION BRD RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| EL4584CSZ-T13 | 功能描述:锁相环 - PLL EL4584CSZ H-SYNC GEN LOCK RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| EL4584CSZ-T7 | 功能描述:锁相环 - PLL EL4584CSZ H-SYNC GEN LOCK RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| EL4585 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Horizontal Genlock, 8FSC |
| EL4585C | 制造商:ELANTEC 制造商全称:ELANTEC 功能描述:Horizontal Genlock, 8 FSC |
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