参数资料
| 型号： | EL5325IRZ-T13 |
| 厂商： | Intersil |
| 文件页数： | 2/11页 |
| 文件大小： | 0K |
| 描述： | IC VREF GEN 12CH TFT-LCD 28-TSSO |
| 标准包装： | 2,500 |
| 应用： | 转换器，TFT，LCD |
| 输入电压： | 5 V ~ 16.5 V |
| 输出数： | 12 |
| 输出电压： | 0.5 V ~ 14.95 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 带卷 (TR) |
EL5325
Absolute Maximum Ratings (T A = 25°C)
Supply Voltage between V S & GND . . . . . . 4.5V (min) to 18V (max)
Supply Voltage between V SD & GND . 3V (min) to V S and 7V (max)
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T J = T C = T A
Electrical Specifications
V S = 15V, V SD = 5V, V REFH = 13V, V REFL = 2V, R L = 1.5k ? and C L = 200pF to 0V, T A = 25°C, unless otherwise
specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
I S
I SD
Supply Current
Digital Supply Current
No load
10.2
0.17
12.5
0.35
mA
mA
ANALOG
V OL
Output Swing Low
Sinking 5mA (V REFH = 15V, V REFL = 0)
50
150
mV
V OH
I SC
PSRR
t D
V AC
? V MIS
V DROOP
R INH
Output Swing High
Short Circuit Current
Power Supply Rejection Ratio
Program to Out Delay
Accuracy referred to the ideal value
Channel to Channel Mismatch
Droop Voltage
Input Resistance @ V REFH , V REFL
Sourcing 5mA (V REFH = 15V, V REFL = 0)
R L = 10 ?
V S + is moved from 14V to 16V
Code = 512
Code = 512
14.85
100
45
14.95
140
65
4
20
2
1
32
2
V
mA
dB
ms
mV
mV
mV/ms
k ?
REG
Load Regulation
I OUT = 5mA step
0.5
1.5
mV/mA
CAP
Band Gap
By pass with 0.1μF
1
1.3
1.6
V
DIGITAL
V IH
F CLK
Logic 1 Input Voltage
Clock Frequency
V SD = 5V
V SD = 3.3V
4
2
5
V
V
MHz
V IL
t S
t H
t LC
t CE
t DCO
R SDIN
T PULSE
Duty Cycle
INL
DNL
F_OSC
Logic 0 Input Voltage
Setup Time
Hold Time
Load to Clock Time
Clock to Load Line
Clock to Out Delay Time
S DIN Input Resistance
Minimum Pulse Width for EXT_OSC Signal
Duty Cycle for EXT_OSC Signal
Integral Nonlinearity Error
Differential Nonlinearity Error
Internal Refresh Oscillator Frequency
V SD = 3.3V/5V
Negative edge of SCLK
OSC_Select = 0
20
20
20
20
10
1
5
50
1.3
0.5
21
1
V
ns
ns
ns
ns
ns
G ?
μs
%
LSB
LSB
kHz
2
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