参数资料
型号: EL5325IRZ-T13
厂商: Intersil
文件页数: 5/11页
文件大小: 0K
描述: IC VREF GEN 12CH TFT-LCD 28-TSSO
标准包装: 2,500
应用: 转换器,TFT,LCD
输入电压: 5 V ~ 16.5 V
输出数: 12
输出电压: 0.5 V ~ 14.95 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 带卷 (TR)
EL5325
Typical Performance Curves (Continued)
M=400μs/DIV
M=400μs/DIV
5V
0V
5V
0V
200mV
0V
SCLK
SDA
OUTPUT
OUTPUT
SCLK
SDA
FIGURE 7. SMALL SIGNAL RESPONSE (RISING FROM 0V
TO 200mV)
FIGURE 8. SMALL SIGNAL RESPONSE (FALLING FROM
200mV TO 0V)
0.9
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
833mW
1.4
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JA
SO
=1 P2
20
°C
JA
SO
C/
0.8
0.7
0.6
0.5
θ
TS
8
/W
1.2
1
0.8
1.333W
θ
TS
=7 P2
W
8
0.4
0.3
0.2
0.1
0.6
0.4
0.2
0
0
25
50
75 85
100
125
0
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 9. POWER DISSIPATION vs AMBIENT
TEMPERATURE
General Description
The EL5325 provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5325,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the eight reference voltage outputs can be set with a
10-bit resolution. These outputs can be driven to within
50mV of the power rails of the EL5325. As all of the output
buffers are identical, it is also possible to use the EL5325 for
applications other than LCDs where multiple voltage
references are required that can be set to 10 bit accuracy.
5
AMBIENT TEMPERATURE (°C)
FIGURE 10. POWER DISSIPATION vs AMBIENT
TEMPERATURE
Digital Interface
The EL5325 uses a simple 3-wire SPI compliant digital
interface to program the outputs. The EL5325 can support
the clock rate up to 5MHz.
Serial Interface
The EL5325 is programmed through a three-wire serial
interface. The start and stop conditions are defined by the
ENA signal. While the ENA is low, the data on the SDI (serial
data input) pin is shifted into the 16-bit shift register on the
positive edge of the SCLK (serial clock) signal. The MSB (bit
15) is loaded first and the LSB (bit 0) is loaded last (see
Table 1). After the full 16-bit data has been loaded, the ENA
is pulled high and the addressed output channel is updated.
The SCLK is disabled internally when the ENA is high. The
SCLK must be low before the ENA is pulled low.
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