参数资料
| 型号： | EL5525IREZ-T13 |
| 厂商： | Intersil |
| 文件页数： | 2/10页 |
| 文件大小： | 0K |
| 描述： | IC VREF GEN 18CH TFTLCD 38HTSSOP |
| 标准包装： | 2,500 |
| 应用： | 转换器，TFT，LCD |
| 输入电压： | 4.5 V ~ 16.5 V |
| 输出数： | 18 |
| 输出电压： | 0.5 V ~ 14.95 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP （0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 38-TSSOP 裸露焊盘 |
| 包装： | 带卷 (TR) |
EL5525
Absolute Maximum Ratings (T A = +25°C)
Supply Voltage
Between V S and GND . . . . . . . . . . . . . . . . 4.5V(min) to 18V(max)
Between V SD and GND . . . . . . . . . . . 3V(min) to V S and +7(max)
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Thermal Information
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
Operating Conditions
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T J = T C = T A
Electrical Specifications
V S = 15V, V SD = 5V, V REFH = 13V, V REFL = 2V, R L = 1.5k Ω and C L = 200pF to 0V, T A = +25°C, unless
otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
I S
I SD
Supply Current
Digital Supply Current
No load
15
0.17
18
0.35
mA
mA
ANALOG
V OL
Output Swing Low
Sinking 5mA (V REFH = 15V, V REFL = 0)
50
150
mV
V OH
I SC
PSRR
t D
V AC
Δ V MIS
V DROOP
R INH
Output Swing High
Short Circuit Current
Power Supply Rejection Ratio
Program to Out Delay
Accuracy Referred to the Ideal Value
Channel to Channel Mismatch
Droop Voltage
Input Resistance @ V REFH , V REFL
Sourcing 5mA (V REFH = 15V, V REFL = 0)
R L = 10 Ω
V S + is moved from 14V to 16V
Code = 512
Code = 512
14.85
100
45
14.95
140
60
4
20
2
1
34
2
V
mA
dB
ms
mV
mV
mV/ms
k Ω
REG
BG
Load Regulation
Band Gap
I OUT = 5mA step
1.1
0.5
1.3
1.5
1.6
mV/mA
V
DIGITAL
V IH
V IL
F CLK
t S
t H
t LC
t CE
Logic 1 Input Voltage
Logic 0 Input Voltage
Clock Frequency
Setup Time
Hold Time
Load to Clock Time
Clock to Load Line
2
20
20
20
20
1
5
V
V
MHz
ns
ns
ns
ns
t DCO
R SDIN
T PULSE
Duty Cycle
F_OSC
INL
DNL
Clock to Out Delay Time
S DIN Input Resistance
Minimum Pulse Width for EXT_OSC
Signal
Duty Cycle for EXT_OSC Signal
Internal Refresh Oscillator Frequency
Integral Nonlinearity Error
Differential Nonlinearity Error
Negative edge of SCLK
OSC_Select = 0
10
1
5
50
21
1.3
0.5
ns
G Ω
μs
%
kHz
LSB
LSB
2
FN7393.2
September 21, 2010
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