参数资料
型号: EL5811IREZ
厂商: Intersil
文件页数: 4/12页
文件大小: 0K
描述: IC AMP 60MHZ R-R 8-CHAN 28HTSSOP
标准包装: 50
放大器类型: 通用
电路数: 8
输出类型: 满摆幅
转换速率: 75 V/µs
增益带宽积: 32MHz
-3db带宽: 60MHz
电流 - 输入偏压: 2nA
电压 - 输入偏移: 3000µV
电流 - 电源: 2.5mA
电流 - 输出 / 通道: 65mA
电压 - 电源,单路/双路(±): 4.5 V ~ 16.5 V,±2.25 V ~ 8.25 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 28-HTSSOP
包装: 管件
12
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FN7355.1
August 3, 2005
when sourcing, and:
when sinking,
where:
i = 1 to 6 for EL5611 and 1 to 8 for EL5811
VS = Total supply voltage
ISMAX = Maximum supply current per amplifier
VOUTi = Maximum output voltage of the application
ILOADi = Load current
If we set the two PDMAX equations equal to each other, we
can solve for RLOADi to avoid device overheat. Figures 29
and 30 provide a convenient way to see if the device will
overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
simple matter to see if PDMAX exceeds the device's power
derating curves. To ensure proper operation, it is important
to observe the recommended derating curves shown in
Figures 29 & 30.
Unused Amplifiers
It is recommended that any unused amplifiers in a dual and
a quad package be configured as a unity gain follower. The
inverting input should be directly connected to the output
and the non-inverting input tied to the ground plane.
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5611 and EL5811 can provide gain at high frequency.
As with any high-frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended, lead lengths
should be as short as possible and the power supply pins
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the VS- pin is
connected to ground, a 0.1F ceramic capacitor should be
placed from VS+ to pin to VS- pin. A 4.7F tantalum
capacitor should then be connected in parallel, placed in the
region of the amplifier. One 4.7F capacitor may be used for
multiple devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are to be
used.
PDMAX
ΣiV
[
S
ISMAX V
(
OUTiVS- )
ILOADi
×
+
×]
=
FIGURE 29. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - HTSSOP
EXPOSED DIEPAD SOLDERED TO PCB PER
JESD51-5
3.5
3
2.5
1.5
1
0.5
0
255075
100
150
AMBIENT TEMPERATURE (°C)
P
O
WER
DIS
S
IPATION
(W
)
3.030W
θJA=33°C/W
HTSSOP24
θJA=30°C/W
HTSSOP28
125
85
2
3.333W
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
0.9
0.6
0.4
0.3
0.2
0.1
0
255075
100
150
AMBIENT TEMPERATURE (°C)
POWE
R
DI
SSI
PATI
ON
(
W
)
85
0.8
0.5
0.7
125
833mW
θJA=120°C/W
HTSSOP24
θJA=110°C/W
HTSSOP28
909mW
EL5611, EL5811
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