参数资料
型号: EL7534IYZ
厂商: Intersil
文件页数: 8/9页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.6A 10MSOP
标准包装: 50
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5.5 V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电压模式
频率 - 开关: 1.5MHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 管件
供应商设备封装: 10-MSOP
产品目录页面: 1242 (CN2011-ZH PDF)
EL7534
I INRMS = ------------------------------------------------ × I O
? I IL = --------------------------------------------
The RMS current present at the input capacitor is decided by
the following formula:
V O × ( V IN - V O )
V IN
This is about half of the output current I O for all the V O . This
input capacitor must be able to handle this current.
The inductor peak-to-peak ripple current is given as:
( V IN - V O ) × V O
L × V IN × f S
? L is the inductance
? f S the switching frequency (nominally 1.5MHz)
The inductor must be able to handle I O for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 1.5A surge current that can occur during a
current limit condition.
Thermal Shut-Down
Once the junction reaches about 145°C, the regulator shuts
down. Both the P channel and the N channel MOSFETs turn
off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will soon cool down.
Once the junction temperature drops to about 130°C, the
regulator will restart again in the same manner as EN pin
connects to logic HI.
Thermal Performance
The EL7534 is in a fused-lead MSOP10 package. Compared
with regular MSOP10 package, the fused-lead package
provides lower thermal resistance. The θ JA is 100°C/W on a
4-layer board and 125°C/W on 2-layer board. Maximizing the
copper area around the pins will further improve the thermal
performance.
Layout Considerations
The layout is very important for the converter to function
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C 4
(Refer to the Typical Application Diagram). The phase-lead
properly. The following PC layout guidelines should be
followed:
? Separate the Power Ground ( ) and Signal Ground (
);
f Z = ----------------------
f P = ---------------------------------------
capacitor creates additional phase margin in the control loop
by generating a zero and a pole in the transfer function. As a
general rule of thumb, C 4 should be sized to start the phase-
lead at a frequency of ~2.5kHz. The zero will always appear
at lower frequency than the pole and follow the equation
below:
1
2 π R 2 C 4
Over a normal range of R 2 (~10-100k), C 4 will range from
~470-4700pF. The pole frequency cannot be set once the
zero frequency is chosen as it is dictated by the ratio of R 1
and R 2 , which is solely determined by the desired output set
point. The equation below shows the pole frequency
relationship:
1
2 π ( R 1 R 2 ) C 4
Current Limit and Short-Circuit Protection
The current limit is set at about 1.5A for the PMOS. When a
short-circuit occurs in the load, the preset current limit
restricts the amount of current available to the output, which
causes the output voltage to drop below the preset voltage.
In the meantime, the excessive current heats up the
regulator until it reaches the thermal shut-down point.
8
connect them only at one point right at the pins
? Place the input capacitor as close to V IN and PGND pins
as possible
? Make the following PC traces as small as possible:
- from L X pin to L
- from C O to PGND
? If used, connect the trace from the FB pin to R1 and R2 as
close as possible
? Maximize the copper area around the PGND pin
? Place several via holes under the chip to additional ground
plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the EL7534 Application Brief.
FN7431.8
July 12, 2006
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