参数资料
型号: EL7563CMZ
厂商: Intersil
文件页数: 11/16页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 4A 20SOIC
标准包装: 38
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1 V ~ 2.5 V
输入电压: 3 V ~ 3.6 V
PWM 型: 电流模式
频率 - 开关: 1MHz
电流 - 输出: 4A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 管件
供应商设备封装: 20-SO
EL7563
T J = 75 + 1.2 – VTJ
Reference
A 1.5% temperature compensated bandgap reference is
integrated in the EL7563. The external V REF capacitor acts
as the dominant pole of the amplifier and can be increased
in size to maximize transient noise rejection. A value of
0.1μF is recommended.
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately 95%.
Operating frequency can be adjusted through the C OSC pin
or can be driven by an external source. If the oscillator is
driven by an external source care must be taken in selecting
the ramp amplitude. Since C SLOPE value is derived from the
C OSC ramp, changes to C OSC ramp will change the
C SLOPE compensation ramp which determine the open-loop
gain of the system.
When external synchronization is required, always choose
C OSC such that the free-running frequency is at least 20%
lower than that of sync source to accommodate component
and temperature variations. Figure 22 shows a typical
connection.
Junction Temperature Sensor
An internal temperature sensor continuously monitors die
temperature. In the event that die temperature exceeds the
thermal trip-point, the system is in fault state and will be shut
down. The upper and low trip-points are set to 135°C and
115°C respectively.
The VTJ pin is an accurate indication of the internal silicon
junction temperature (see performance curve.) The junction
temperature T J (°C) can be deducted from the following
relation:
-------------------------
0.00384
Where VTJ is the voltage at VTJ pin in volts.
Power Good and Power On Reset
During power up the output regulator will be disabled until
V IN reaches a value of approximately 2.9V. About 300mV
hysteresis is present to eliminate noise-induced
oscillations.
Under-voltage and over-voltage conditions on the regulator
output are detected through an internal window comparator.
1
20
A logic high on the PG output indicates that the regulated
output voltage is within about +10% of the nominal selected
100pF
BAT54S
2
19
output voltage.
EXTERNAL
OSCILLATOR
390pF
3
5
18
16
6
7
8
9
10
EL7563
15
14
13
12
11
FIGURE 22. OSCILLATOR SYNCHRONIZATION
11
FN7296.2
May 13, 2005
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