参数资料
| 型号： | EL7571CM |
| 厂商： | Intersil |
| 文件页数： | 3/19页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM PROGRAMMABLE 20SOIC |
| 标准包装： | 38 |
| 应用： | 控制器，Intel Pentium? II，Pro |
| 输入电压： | 4.5 V ~ 12.6 V |
| 输出数： | 2 |
| 输出电压： | 1.3 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SO |
| 包装： | 管件 |
EL7571
DC Electrical Specifications
T A = 25°C, V IN = 5V, C OSC = 330pF, C SLOPE = 390pF, R SENSE = 7.5m ? unless otherwise specified.
(Continued)
PARAMETER
I VID
I OTEN
DESCRIPTION
VID Input Pull up Current
OTEN Input Pull up Current
CONDITION
MIN
3
3
TYP
5
5
MAX
7
7
UNIT
μA
μA
AC Electrical Specifications
T A = 25°C, V IN = 5V, C OSC = 330pF, C SLOPE = 390pF unless otherwise specified.
PARAMETER
f OSC
f CLK
t OTEN
t SYNC
DESCRIPTION
Nominal Oscillator Frequency
Clock Frequency
Shutdown Delay
Oscillator Sync. Pulse Width
CONDITIONS
C OSC = 330pF
V OTEN >1.5V
Oscillator i/p (COSC) driven with
MIN
140
50
20
TYP
190
500
100
MAX
240
1000
800
UNIT
kHz
kHz
ns
ns
HCMOS gate
T START
D MAX
Soft-start Period
Maximum Duty Cycle
V OUT = 3.5V
100/f CLK
97
us
%
Pin Descriptions
PIN TYPE
PIN NO.
1
2
PIN NAME
OTEN
CSLOPE
(NOTE 1)
I
I
FUNCTION
Chip enable input, internal pull up (5mA typical). Active high.
With a capacitor attached from CSLOPE to GND, generates the voltage ramp compensation for the PWM
current mode controller. Slope rate is determined by an internal 14uA pull up and the C SLOPE capacitor
value. VC SLOPE is reset to ground at the termination of the high side cycle.
3
COSC
I
Multi-function pin: with a timing capacitor attached, sets the internal oscillator rate f S (kHz) = 57/C OSC (μF);
when pulsed low for a duration t SYNC synchronizes device to an external clock.
4
5
REF
PWRGD
O
O
Band gap reference output. Decouple to GND with 0.1uF.
Power good, open drain output. Set low whenever the output voltage is not within ±13% of the programmed
value.
6
7
8
9
10
11
12
VID0
VID1
VID2
VID3
VID4
FB
CS
I
I
I
I
I
I
I
Bit 0 of the output voltage select DAC. Internal pull up sets input high when not driven.
Bit 1 of the output voltage select DAC. Internal pull up sets input high when not driven.
Bit 2 of the output voltage select DAC. Internal pull up sets input high when not driven.
Bit 3 of the output voltage select DAC. Internal pull up sets input high when not driven.
Bit 4 of the output voltage select DAC. Internal pull up sets input high when not driven.
Voltage regulation feedback input. Tie to V OUT for normal operation.
Current sense. Current feedback input of PWM controller and over current capacitor input. Current limit
threshold set at +154mV with respect to FB. Connect sense resistor between CS and FB for normal
operation.
13
14
15
16
17
18
19
GND
GNDP
LSD
VINP
VIN
LX
HSD
S
S
O
S
S
S
O
Ground
Power ground for low side FET driver. Tie to GND for normal operation.
Low side gate drive output.
Input supply voltage for low side FET driver. Tie to VIN for normal operation.
Input supply voltage for control unit.
Negative supply input for high side FET driver.
High side gate drive output. Driver ground referenced to LX. Driver supply may be bootstrapped to enhance
low controller input voltage operation.
20
VH1
S
Positive supply input for high side FET driver.
NOTE: Pin designators: I = Input, O = Output, S = Supply
3
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