参数资料
型号: EL7586AILZ-T13
厂商: Intersil
文件页数: 4/21页
文件大小: 0K
描述: IC POWER SUPPLY TFT-LCD 20-QFN
标准包装: 2,500
应用: 转换器,TFT,LCD
输入电压: 3 V ~ 5 V
输出数: 4
输出电压: 5.5 V ~ 20 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-VFQFN 裸露焊盘
供应商设备封装: 20-QFN 裸露焊盘(4x4)
包装: 带卷 (TR)
EL7586, EL7586A
Electrical Specifications
V DD = 5V, V BOOST = 11V, I LOAD = 200mA, V ON = 15V, V OFF = -5V, V LOGIC = 2.5V, over temperature from
-40°C to 85°C, unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
FAULT DETECTION
t FAULT
OT
I PG
Fault Time Out
Over-temperature Threshold
PG Pull-down Current
C DLY = 0.22μF
VPG > 0.6V
VPG < 0.6V
50
140
15
1.7
ms
°C
μA
mA
LOGIC ENABLE
V HI
V LO
Logic High Threshold
Logic Low Threshold
2.3
0.8
V
V
I LOW
Logic Low Bias Current
0.2
2
μA
I HIGH
Logic High Bias Current
at V EN = 5V
12
18
24
μA
Pin Descriptions
PIN NAME
1
2
3, 4
5
6
7
8
9, 17
10
11
12, 13
14
15
16
18
19
20
PIN NUMBER
CDLY
DELB
LX1, LX2
DRVP
FBP
DRVL
FBL
SGND
DRVN
FBN
PGND
VREF
CINT
FBB
EN
VDD
PG
4
DESCRIPTION
A capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault
timeout time
Open drain output for gate drive of optional V BOOST delay FET
Drain of the internal N channel boost FET; for EL7586, pin 4 is not connected
Positive LDO base drive; open drain of an internal N channel FET
Positive LDO voltage feedback input pin; regulates to 1.2V nominal
Logic LDO base drive; open drain of an internal N channel FET
Logic LDO voltage feedback input pin; regulates to 1.2V nominal
Low noise signal ground
Negative LDO base drive; open drain of an internal P channel FET
Negative LDO voltage feedback input pin; regulates to 0.2V nominal
Power ground, connected to source of internal N channel boost FET
Bandgap voltage bypass, connect a 0.1μF to SGND
V BOOST integrator output, connect capacitor to SGND for PI mode or connect to V DD for P mode
operation
Boost regulator voltage feedback input pin; regulates to 1.2V nominal
Enable pin, High = Enable; Low or floating = Disable
Positive supply
Push-pull gate drive of optional fault protection FET, when chip is disabled or when a fault has been
detected, this is high
FN9210.2
January 17, 2006
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