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参数资料
| 型号： | EL9115ILZ-T13 |
| 厂商： | Intersil |
| 文件页数： | 3/10页 |
| 文件大小： | 0K |
| 描述： | IC ANALOG DELAY LINE TRPL 20-QFN |
| 标准包装： | 2,500 |
| 类型： | 视频延迟线 |
| 应用： | 模拟波速合成，失真控制 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN（5x5） |
| 包装： | 带卷 (TR) |
2
FN7441.7
January 12, 2012
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Conditions
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Resistance (Typical)
θJA (°C/W)
20 Ld QFN Package (Note 4). . . . . . . . . . . . . . . . . .
32
Power Dissipation . . See “Typical Performance Curves” on page 4.
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
4.
θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
DC Electrical Specifications
VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, exposed die plate = -5V, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
V+
Positive Supply Range
+4.5
+5.5
V
V-
Negative Supply Range
-4.5
-5.5
V
G_0
Gain Zero Delay
X2 = 5V, 150
Ω load
1.81
1.9
2.04
G_m
Gain Mid Delay
1.64
1.8
1.97
G_f
Gain Full Delay
1.46
1.7
1.97
DG_m0
Difference in Gain, 0 to Mid
-10
-4
2.3
%
DG_f0
Difference in Gain, 0 to Full
-17.5
-9
0.3
%
DG_fm
Difference in Gain, Mid to Full
-15
-5
4
%
VIN
Input Voltage Range
Gain falls to 90% of nominal
-0.7
1.2
V
IB
Input Bias Current
15
A
RIN
Input Resistance
10
M
Ω
VOS_0
Output Offset 0 Delay
X2 = +5V, 75 + 75
Ω load
-90
0
90
mV
VOS_M
Output Offset Mid Delay
-90
0
90
mV
VOS_F
Output Offset Full Delay
-90
0
90
mV
ZOUT
Output Impedance
Chip enable = +5V
4.5
5
6.3
Ω
Chip enable = 0V
1
M
Ω
+PSRR
Rejection of Positive Supply
X2 = +5V into 75 + 75
Ω load
-38
dB
-PSRR
Rejection of Negative Supply
X2 = +5V into 75 + 75
Ω load
-53
dB
ISP
Supply Current (Note 5)
Chip enable = +5V current on VSP
75
87
115
mA
ISM
Supply Current (Note 5)
Chip enable = +5V current in VSM
-15.25
-12.5
-9.75
mA
ISMO
Supply Current (Note 5)
Chip enable = +5V current in VSMO
-15.25
-13
-11
mA
ISPO
Supply Current (Note 5)
Chip enable = +5V current in VSPO
10
11.8
15.5
mA
ΔISP
Supply Current (Note 5)
Increase in ISP per unit step in delay
0.9
mA
ISP OFF
Supply Current (Note 5)
Chip enable = 0V current in VSP
1.6
mA
IOUT
Output Drive Current
10
Ω load, 0.5V drive, X2 = 5V
40
mA
LHI
Logic High
Switch high threshold
1.25
1.6
V
LLO
Logic Low
Switch low threshold
0.8
1.15
V
EL9115
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