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参数资料
| 型号： | EM78459 |
| 英文描述： | Dual Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 14-SOIC |
| 中文描述： | 8位微控制器的通用产品 |
| 文件页数： | 21/57页 |
| 文件大小： | 854K |
| 代理商： | EM78459 |
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EM78458/459
MASK ROM
This specification is subject to change without prior notice.
2002/03/01
28
4.6 Interrupt
The EM78458/459 has six interrupts as listed below:
(1) TCC overflow interrupt
(2) Port 6 Input Status Change Interrupt
(3) External interrupt [(P50, /INT) pin].
(4) Analog to Digital conversion completed.
(5) When TMR1/TMR2 matches with PRD1/PRD2 respectively in PWM.
(6) When the comparators output changes.
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g. "MOV R6,R6") is
necessary. Each Port 6 pin will have this feature if its status changes. Any pin configured as output or
P50 pin configured as /INT, is excluded from this function. Port 6 Input Status Change Interrupt will
wake up the EM78458/459 from the sleep mode if it is enabled prior to going into the sleep mode by
executing SLEP. When the controller is wa ke-up, it will continue to execute the succeeding program if
the global interrupt is disabled, or branches out to the interrupt vector 008H if the global interrupt is
enabled.
RF, the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF0 is
an interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the
DISI instruction. When one of the interrupts (when enabled) occurs, the next instruction will be
fetched from address 008H. Once in the interrupt service routine, the source of an interrupt can be
determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before
leaving the interrupt service routine to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the status of its
mask bit or the execution of ENI. Note that the outcome of RF will be the logic AND of RF and IOCF0
(refer to Fig. 11). The RETI instruction ends the interrupt routine and enables the global interrupt (the
execution of ENI).
When an interrupt is generated by the INT instruction (when enabled), the next instruction will be
fetched from address 001H.
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