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参数资料
| 型号： | EM78459 |
| 英文描述： | Dual Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 14-SOIC |
| 中文描述： | 8位微控制器的通用产品 |
| 文件页数： | 45/57页 |
| 文件大小： | 854K |
| 代理商： | EM78459 |
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EM78458/459
MASK ROM
This specification is subject to change without prior notice.
2002/03/01
5
PWM2
* Defined by PWMCON (IOC51)<6, 7>
VREF
15
I
* External reference voltage for ADC
* Defined by AD-CMPCON (IOCA0)<7>.
CIN-, CIN+,
CO
20, 1,2
I
O
* “-“ -> the input pin of Vin- of the comparator.
* “+”-> the input pin of Vin+ of the comparator.
* Pin CO is the output of the comparator.
* Defined by AD-CMPCON (IOCA0) <5, 6>
TCC
19
I
* Real time clock/counter with Schmitt trigger input pin; it must be tied to
VDD or VSS if it is not in use.
VSS
5
-
Ground.
Table 2 EM78459 Pin Description
Symbol
Pin No.
Type
Function
VDD
19, 18
-
Power supply.
OSCI
22
I
* XTAL type: Crystal input terminal or external clock input pin.
* RC type: RC oscillator input pin.
OSCO
21
O
* XTAL type: Output terminal for crystal oscillator or external clock input
pin.
* RC type: Clock output with a period of one instruction cycle time, the
prescaler is determined by the CONT register.
* External clock signal input.
P50
14
I
* General-purpose Input only.
* Default value while power-on reset.
P51 ~ P57
15~17
23, 24
1, 2
I/O
* General-purpose I/O pin.
* Default value while power-on reset.
P60 ~ P67
3, 4,
8~13
I/O
* General-purpose I/O pin.
* Default value while power-on reset.
INT
14
I
* External interrupt pin triggered by falling edge.
ADC1~ADC8
3, 4,
8~13
I
* Analog to Digital Converter.
* Defined by AD-CMPCON (IOCA0)<2:4>.
PWM1,
PWM2
15, 16
O
* Pulse width modulation outputs.
* Defined by PWMCON (IOC51)<6, 7>
VREF
17
I
* External reference voltage for ADC
* Defined by AD-CMPCON (IOCA0)<7>.
CIN-, CIN+,
CO
24, 1, 2
I
* ‘-’ -> the Vin- input pins of the comparators.
* ‘+’ -> the Vin+ input pins of the comparators.
* Pin CO is the output of the comparator.
* Defined by AD-CMPCON (IOCA0) <5, 6>
/RESET
20
I
* If it remains at logic low, the device will be reset.
* Wake up from sleep mode when pins status changes.
* Voltage on /RESET/Vpp must not be over Vdd during normal mode.
* Pull-high is on if /RESET is asserted.
TCC
23
I
* Real time clock/counter with Schmitt trigger input pin; it must be tied to
VDD or VSS if it is not in use.
ENTCC
5
I
1: Enable TCC; 0: Disable TCC.
VSS
6, 7
-
Ground.
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