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| 型号： | EM78P451 |
| 英文描述： | Dual Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features; Temperature Range: 0°C to 70°C; Package: 16-QFN |
| 中文描述： | 8位微控制器的通用产品[英文] |
| 文件页数： | 2/52页 |
| 文件大小： | 1287K |
| 代理商： | EM78P451 |
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EM78P451
OTP ROM
This specification is subject to change without prior notice.
2002/03/01
10
8. RA (SPIRB: SPI Read Buffer)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0X0A
SPIRB/RA
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB7~SRB0 are the 8-bit data when complete transmission by SPI.
9. RB (SPIWB: SPI Write Buffer)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0B
SPIWB/RB
SWB7
SWB6
SWB5
SWB4
SWB3
SWB2
SWB1
SWB0
SWB7~SWB0 are the 8-bit data that are waiting for transmission by SPI.
10. RC (SPIS: SPI Status Segister)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0C
SPIS/RC
--
TM1IF
OD3
OD4
RBFIF
RBF
TM1IF (bit 4):
1 = In timer1 mode, receiving completed, and an interrupt occurs if enabled.
0 = In timer1 mode, receiving not completed yet, and an interrupt does not occur.
OD3 (bit 3):Open-Drain Control bit
1 = Open-drain enable for SDO,
0 = Open-drain disable for SDO.
OD4 (bit 2):Open-Drain Control bit
1 = Open-drain enable for SCK,
0 = Open-drain disable for SCK.
RBFIF (bit 1):Read Buffer Full Interrupt Flag
1 = Receiving completed, SPIRB is fully exchanged, and an interrupt occurs if enabled.
0 = Receiving not completed yet; and SPIRB has not fully exchanged.
RBF (bit 0): Read Buffer Full flag
1 = Receiving completed; SPIRB is fully exchanged.
0 = Receiving not completed yet, and SPIRB has not fully exchanged.
11. RD (SPIC: SPI Control Register)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0D
SPIC/RD
CES
SPIE
SRO
SSE
-
SBRS2
SBRS1 SBRS0
CES (bit 7): Clock Edge Select bit
1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold during the high level.
0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold during the low level.
SPIE (bit 6): SPI Enable bit
1= Enable SPI mode
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